From: Vidya Sagar <vidyas@nvidia.com>
To: <lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <kishon@ti.com>, <vkoul@kernel.org>,
<mani@kernel.org>, <Sergey.Semin@baikalelectronics.ru>,
<ffclaire1224@gmail.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V1 9/9] PCI: tegra194: Calibrate P2U for endpoint mode
Date: Mon, 19 Sep 2022 20:06:27 +0530 [thread overview]
Message-ID: <20220919143627.13803-10-vidyas@nvidia.com> (raw)
In-Reply-To: <20220919143627.13803-1-vidyas@nvidia.com>
Calibrate P2U for endpoint to request UPHY PLL rate change to Gen1 during
initialization.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 35d9c3ac3028..67dd97f3cd6e 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1078,6 +1078,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
ret = phy_power_on(pcie->phys[i]);
if (ret < 0)
goto phy_exit;
+
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+ phy_calibrate(pcie->phys[i]);
}
return 0;
--
2.17.1
prev parent reply other threads:[~2022-09-19 14:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-19 14:36 [PATCH V1 0/9] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 1/9] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 2/9] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 3/9] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 4/9] PCI: tegra194: Handle errors in BPMP response Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 5/9] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 6/9] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 7/9] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-09-19 14:36 ` [PATCH V1 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-09-19 16:33 ` kernel test robot
2022-09-20 6:11 ` Vinod Koul
2022-09-19 14:36 ` Vidya Sagar [this message]
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