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Fri, 28 Oct 2022 05:34:01 -0700 From: Jon Hunter To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= CC: , , Jon Hunter Subject: [PATCH V2 1/2] pwm: tegra: Improve required rate calculation Date: Fri, 28 Oct 2022 13:33:55 +0100 Message-ID: <20221028123356.133796-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-NVConfidentiality: public Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT035:EE_|BL1PR12MB5850:EE_ X-MS-Office365-Filtering-Correlation-Id: a24f72e0-ee67-4ab4-e629-08dab8e0b7b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iedDWrYx5VC/7LbPKgm7tDLTmvcfipN7s7+9KCQ6cS/Rb+uIN28loWpi7EZGA9sRZaoXE0qdP84xTZ/6++FfLz2Rf15NSmwwiAUajGLtjGqQj8vpU709VW27wvvzXtheDxCQMuw6IBZfSWJFeVR5Gku6GHYFptAnAzrkqaG+qMD9D9Dqyp/0ClE7D0w3nytk5OZkZLbbX0Rbu8RtKQpejayDU02nkocX7Yi0CM6m5Piv2w8AIRW2ZJ5PW9AaQKp+vtVa2K//cASLePUWmqXzeH+1//Q3sJk2yO4/mBQh671DVKQAqI3VDOLPYR4OPIuyVI9n1SG5t1jGexQaklML2e8r/iC/s9kuqC8vV20bMyrt907FthfwfRUTQO9tEnVPOEC6Tie5ch8AU3ZXheEPqeRDYfVUmioIBWW/fS7XivDnWP3Qoj+CHwt1b2xPpCtsXXjWURpToNmF+LfD/+/mSRjqMpxT7bsBk9dd0xtG46bb/YmIhdW5S+VVW5dUc30luLfMpdl81fQkD7Rf6lYnUJTHSUfFbBf1mdaDUCW/9Fkv7S2I3hrfiCpMlix5SmKKZGQQNYGwBUfHz5mo78FJ8nJIDSrKYqdS6fw6eoF+PX8HrWWvDL/JeLKGZeFBYoEkJlMO4OxGVYadmIteEBI1FyDCQQtblkTAdTzi+td/ifKtw5VMm5cWxy6a23T26sdQNSD3QR7O9tTZQrERMWTxFpoN6wGt0iBBvDNtISCNjUHl6fwG2w5ThdmGiv5GNdl63H2AL+eqk4X+zkKVlMRQSA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(346002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(36756003)(82740400003)(86362001)(8936002)(7636003)(356005)(40460700003)(40480700001)(110136005)(316002)(54906003)(478600001)(4326008)(70206006)(70586007)(8676002)(2906002)(41300700001)(82310400005)(5660300002)(47076005)(186003)(336012)(36860700001)(426003)(26005)(1076003)(6666004)(83380400001)(107886003)(2616005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2022 12:34:11.9942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a24f72e0-ee67-4ab4-e629-08dab8e0b7b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5850 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org For the case where dev_pm_opp_set_rate() is called to set the PWM clock rate, the requested rate is calculated as ... required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; The above calculation may lead to rounding errors because the NSEC_PER_SEC is divided by 'period_ns' before applying the PWM_DUTY_WIDTH multiplication factor. For example, if the period is 45334ns, the above calculation yields a rate of 5646848Hz instead of 5646976Hz. Fix this by applying the multiplication factor before dividing and using the DIV_ROUND_UP macro which yields the expected result of 5646976Hz. Fixes: 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration") Signed-off-by: Jon Hunter Reviewed-by: Uwe Kleine-König --- Changes since V1: - Dropped extra parenthesis drivers/pwm/pwm-tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index dad9978c9186..b05ea2e8accc 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -145,8 +145,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate = - (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH; + required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH, + period_ns); err = dev_pm_opp_set_rate(pc->dev, required_clk_rate); if (err < 0) -- 2.25.1