From: Besar Wicaksono <bwicaksono@nvidia.com>
To: <acme@redhat.com>, <catalin.marinas@arm.com>, <will@kernel.org>,
<john.g.garry@oracle.com>, <james.clark@arm.com>,
<mike.leach@linaro.org>, <peterz@infradead.org>,
<mingo@redhat.com>, <mark.rutland@arm.com>,
<alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>,
<namhyung@kernel.org>, <irogers@google.com>,
<alisaidi@amazon.com>, <vsethi@nvidia.com>, <rwiley@nvidia.com>,
<ywan@nvidia.com>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-perf-users@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<treding@nvidia.com>, <jonathanh@nvidia.com>,
Besar Wicaksono <bwicaksono@nvidia.com>
Subject: [PATCH v1 2/3] tools headers arm64: Add Neoverse-V2 part
Date: Tue, 9 Jan 2024 13:23:09 -0600 [thread overview]
Message-ID: <20240109192310.16234-3-bwicaksono@nvidia.com> (raw)
In-Reply-To: <20240109192310.16234-1-bwicaksono@nvidia.com>
Add the part number and MIDR for Neoverse-V2.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
index 7c7493cb571f..fe13a25fa082 100644
--- a/tools/arch/arm64/include/asm/cputype.h
+++ b/tools/arch/arm64/include/asm/cputype.h
@@ -85,6 +85,7 @@
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
+#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -156,6 +157,7 @@
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.17.1
next prev parent reply other threads:[~2024-01-09 19:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 19:23 [PATCH v1 0/3] arm64: Support Neoverse-V2 for Perf Arm SPE Besar Wicaksono
2024-01-09 19:23 ` [PATCH v1 1/3] arm64: Add Neoverse-V2 part Besar Wicaksono
2024-01-09 19:23 ` Besar Wicaksono [this message]
2024-01-09 19:23 ` [PATCH v1 3/3] perf arm-spe: Add Neoverse-V2 to neoverse list Besar Wicaksono
2024-01-10 1:14 ` Leo Yan
2024-01-10 9:12 ` [PATCH v1 0/3] arm64: Support Neoverse-V2 for Perf Arm SPE James Clark
2024-04-15 15:56 ` Besar Wicaksono
2024-04-30 17:50 ` Besar Wicaksono
2024-04-30 20:26 ` Leo Yan
2024-04-19 15:32 ` Will Deacon
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