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From: "Krzysztof Wilczyński" <kw@linux.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Niklas Cassel <cassel@kernel.org>,
	Vidya Sagar <vidyas@nvidia.com>,
	linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org,
	Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: Re: [PATCH V2] PCI: tegra194: Set EP alignment restriction for inbound ATU
Date: Fri, 17 May 2024 20:31:05 +0900	[thread overview]
Message-ID: <20240517113105.GB202520@rocinante> (raw)
In-Reply-To: <20240508092207.337063-1-jonathanh@nvidia.com>

Hello,

> Tegra194 and Tegra234 PCIe EP controllers have 64K alignment
> restriction for the inbound ATU. Set the endpoint inbound ATU alignment to
> 64kB in the Tegra194 PCIe driver.

Applied to controller/tegra194, thank you!

[1/1] PCI: tegra194: Set EP alignment restriction for inbound ATU
      https://git.kernel.org/pci/pci/c/ff58a429d70c

	Krzysztof

      parent reply	other threads:[~2024-05-17 11:31 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-08  9:22 [PATCH V2] PCI: tegra194: Set EP alignment restriction for inbound ATU Jon Hunter
2024-05-08  9:27 ` Niklas Cassel
2024-05-15 21:21   ` Bjorn Helgaas
2024-05-17 11:31 ` Krzysztof Wilczyński [this message]

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