Linux Tegra architecture development
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From: "Sheetal ." <sheetal@nvidia.com>
To: <broonie@kernel.org>, <linux-sound@vger.kernel.org>
Cc: <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<jonathanh@nvidia.com>, <thierry.reding@gmail.com>,
	<mkumard@nvidia.com>, <spujar@nvidia.com>,
	Sheetal <sheetal@nvidia.com>
Subject: [PATCH 10/10] ASoC: tegra: Tegra264 support in isomgr_bw
Date: Tue, 22 Apr 2025 07:28:05 +0000	[thread overview]
Message-ID: <20250422072805.501152-11-sheetal@nvidia.com> (raw)
In-Reply-To: <20250422072805.501152-1-sheetal@nvidia.com>

From: Sheetal <sheetal@nvidia.com>

Tegra264 supports max 32 channels, hence calculating the max
bandwidth using the channel info from soc_data.

Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 sound/soc/tegra/tegra_isomgr_bw.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/sound/soc/tegra/tegra_isomgr_bw.c b/sound/soc/tegra/tegra_isomgr_bw.c
index 18e802bca6a6..fa979960bc09 100644
--- a/sound/soc/tegra/tegra_isomgr_bw.c
+++ b/sound/soc/tegra/tegra_isomgr_bw.c
@@ -11,8 +11,8 @@
 #include "tegra_isomgr_bw.h"
 #include "tegra210_admaif.h"
 
-/* Max possible rate is 192KHz x 16channel x 4bytes */
-#define MAX_BW_PER_DEV 12288
+#define MAX_SAMPLE_RATE		192	/* KHz*/
+#define MAX_BYTES_PER_SAMPLE	4
 
 int tegra_isomgr_adma_setbw(struct snd_pcm_substream *substream,
 			    struct snd_soc_dai *dai, bool is_running)
@@ -98,7 +98,8 @@ int tegra_isomgr_adma_register(struct device *dev)
 	}
 
 	adma_isomgr->max_pcm_device = admaif->soc_data->num_ch;
-	adma_isomgr->max_bw = STREAM_TYPE * MAX_BW_PER_DEV * adma_isomgr->max_pcm_device;
+	adma_isomgr->max_bw = STREAM_TYPE * MAX_SAMPLE_RATE * MAX_BYTES_PER_SAMPLE *
+			      admaif->soc_data->max_stream_ch * adma_isomgr->max_pcm_device;
 
 	for (i = 0; i < STREAM_TYPE; i++) {
 		adma_isomgr->bw_per_dev[i] = devm_kzalloc(dev, adma_isomgr->max_pcm_device *
-- 
2.17.1


      parent reply	other threads:[~2025-04-22  7:29 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-22  7:27 [PATCH 00/10] Add Tegra264 support in AHUB drivers Sheetal .
2025-04-22  7:27 ` [PATCH 01/10] dt-bindings: ASoC: Document Tegra264 APE support Sheetal .
2025-04-23 12:46   ` Krzysztof Kozlowski
     [not found]     ` <22d4729d-590d-4082-ad02-7d4fdbfd08b6@nvidia.com>
2025-04-24  8:50       ` Krzysztof Kozlowski
2025-04-22  7:27 ` [PATCH 02/10] ASoC: tegra: CIF: Add Tegra264 support Sheetal .
2025-04-22  7:27 ` [PATCH 03/10] ASoC: tegra: ADMAIF: " Sheetal .
2025-04-22  7:27 ` [PATCH 04/10] ASoC: tegra: ASRC: Update ARAM address Sheetal .
2025-04-22  7:28 ` [PATCH 05/10] ASoC: tegra: Update PLL rate for Tegra264 Sheetal .
2025-04-22  7:28 ` [PATCH 06/10] ASoC: tegra: I2S: Add Tegra264 support Sheetal .
2025-04-22  7:28 ` [PATCH 07/10] ASoC: tegra: AMX: " Sheetal .
2025-04-22  7:28 ` [PATCH 08/10] ASoC: tegra: ADX: " Sheetal .
2025-04-22  7:28 ` [PATCH 09/10] ASoC: tegra: AHUB: " Sheetal .
2025-04-22  7:28 ` Sheetal . [this message]

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