From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <treding@nvidia.com>,
Sasha Levin <sashal@kernel.org>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
thierry.reding@gmail.com, dstotland@nvidia.com,
bgriffis@nvidia.com, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: [PATCH AUTOSEL 6.6 105/294] arm64: tegra: Resize aperture for the IGX PCIe C5 slot
Date: Mon, 5 May 2025 18:53:25 -0400 [thread overview]
Message-ID: <20250505225634.2688578-105-sashal@kernel.org> (raw)
In-Reply-To: <20250505225634.2688578-1-sashal@kernel.org>
From: Jon Hunter <jonathanh@nvidia.com>
[ Upstream commit 6d4bfe6d86af1ef52bdb4592c9afb2037f24f2c4 ]
Some discrete graphics cards such as the NVIDIA RTX A6000 support
resizable BARs. When connecting an A6000 card to the NVIDIA IGX Orin
platform, resizing the BAR1 aperture to 8GB fails because the current
device-tree configuration for the PCIe C5 slot cannot support this.
Fix this by updating the device-tree 'reg' and 'ranges' properties for
the PCIe C5 slot to support this.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20250116151903.476047-1-jonathanh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
.../boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
index bac611d735c58..2fa48972b2a91 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
@@ -102,6 +102,16 @@ pcie@14160000 {
};
pcie@141a0000 {
+ reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
+ 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
+ 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
+ 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
+ 0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB) */
+
+ ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
+ 0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000 /* non-prefetchable memory (128MB) */
+ 0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>; /* prefetchable memory (25088MB) */
+
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
--
2.39.5
next prev parent reply other threads:[~2025-05-05 23:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250505225634.2688578-1-sashal@kernel.org>
2025-05-05 22:52 ` [PATCH AUTOSEL 6.6 074/294] pinctrl-tegra: Restore SFSEL bit when freeing pins Sasha Levin
2025-05-05 22:53 ` [PATCH AUTOSEL 6.6 100/294] cpufreq: tegra186: Share policy per cluster Sasha Levin
2025-05-05 22:53 ` [PATCH AUTOSEL 6.6 104/294] arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator Sasha Levin
2025-05-05 22:53 ` Sasha Levin [this message]
2025-05-05 22:53 ` [PATCH AUTOSEL 6.6 111/294] ARM: tegra: Switch DSI-B clock parent to PLLD on Tegra114 Sasha Levin
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