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Thu, 19 Jun 2025 01:44:37 -0700 From: Shubhi Garg To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Catalin Marinas" , Will Deacon , "Alexandre Belloni" , Jonathan Hunter CC: , , , , Shubhi Garg Subject: [PATCH v4 0/6] Add NVIDIA VRS PSEQ support Date: Thu, 19 Jun 2025 08:44:21 +0000 Message-ID: <20250619084427.3559207-1-shgarg@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|IA1PR12MB7711:EE_ X-MS-Office365-Filtering-Correlation-Id: b60df655-ed4f-40a6-8592-08ddaf0d900d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8BsCwN02nCqsx+e1gdTggiWp6leR3EA5MeHo5DD5I6dV+v45usgwbjZGszCc?= =?us-ascii?Q?+6+6tyFRtLUvPeNqIij0kDx77r6rMjieBcGdpPVAN4j6NiRYLlAP/cv9XVW5?= =?us-ascii?Q?RgxvliSUhfW9MFwg8BwDu7h5XrXK+WjTof9OkLJJHT9QnhFPiRsoN+2EF+x8?= =?us-ascii?Q?HVjNk7QI8cjVv9JknSg6/4DF7Ihwc8LkdWuuMIpquL2a5CPRN9sjSKGxlhiC?= =?us-ascii?Q?Yd1lcKBvS2zoRghMtVBGJ/0kUKJLrlQe+AIqEnB8TlYPY31K/u2yevV/0E9B?= =?us-ascii?Q?+qFZI0HAQ4jQXCuIs8Oz87CF8wm+l+EMq7Z/4OWHRWKDNbaT6XLK9G5nX6g+?= =?us-ascii?Q?qntzldZeppHnXRmbjSOASBfljPDVFXvMgjHmeS8s7CvNQ3Bo81jUsoXUADja?= =?us-ascii?Q?GqReGjgoNq7DoXCcRAVcNzIFe3pzvfD+stCatbKm7Wg9HR0komWbu3R1FouL?= =?us-ascii?Q?SfXiRJYOf8MOoEtrFRD7kPMvNVrDEBP444J7BtFEERgIynslrdh3d+p4zVdq?= =?us-ascii?Q?jWb9zhb+VAlzsUngT2kjUpFLgOrDFnpK/zFp3GIRrWG18iPUKaonI9MIpCy5?= =?us-ascii?Q?pbzpzAsOgrMFs4Vy6qut6g8hcatF2sxVo9tYfJB9hQFt8A0qWJVAUQ6BJlqh?= =?us-ascii?Q?O1hcxM1Q3Gx9JbHKCivuPQ1UDZ2JAC+VSdN1nthhRtUz1xChdtNnBO2UYmbb?= =?us-ascii?Q?+KfPAh5uGT9rWs6/7sGiQk2v0m5B4JLuvN4LH7y6vGx2T/YpuvAbOnvrz+hb?= =?us-ascii?Q?euwlN9+p/2Pco6NtfxWiWRnPgFgm32nPibXXVKszYxqlgR1yDASeouWqeGtK?= =?us-ascii?Q?+5m73mjvK1xABlRDV5lYtyN3ShPQHTh4SAaefb+D/2jmJNGeJ+2VhDAQqEY3?= =?us-ascii?Q?OyYmirDL+BLqxmtD6CVDKPdlFapqY0sX3pR/RVDkIL3CVV9EGoOgkTxh29k4?= =?us-ascii?Q?yt0VyABJyNVQ4Kvtgoz7bUE/+dArmfGOiVhdDZKPblnfGxud1gsO5GwFikW7?= =?us-ascii?Q?k6Iq2I+AzQJSgHtNOMvpRFnECKdxj5viqfa/H4Mdz2mSR2msZAiDN4pAp1sP?= =?us-ascii?Q?rRjPqNLV1COgyXAnLtOkVmhvEkShRluTq0I0SeFhFxhSrEondCecmawf5akx?= =?us-ascii?Q?WBorickVafsuMtAiGdxVZgXgIdYsACvMtc8ceEbmGqOPC/u2f3D+P4w82XI4?= =?us-ascii?Q?d/MLndzPlaWxX3kvzDEFZwbFj0EmztzgMLbP0P36OaLzEnOh4oaCFwreZIc3?= =?us-ascii?Q?XxfWHwyyuYw7qcVhoq7anP76fAZxE+o2600JswuZl9LnwiHhaf+fO9UFFnf6?= =?us-ascii?Q?uWyWpGYFNDg/4CkjD/ieZW5pTGe+SZx4u0jNqZ1QfXDW9hghRF4oyc35DOEX?= =?us-ascii?Q?NrPnnVsSI8LVf8O5Mix42bMNOvF6gV+qO7NXOt6RTYctw2MhfB5m16QGMYam?= =?us-ascii?Q?e91WU6KXd+2Fjg/t0kPEBQJvyRmWIlWw1Fduca2fg0Uxl+6GgQgJHTdhlifo?= =?us-ascii?Q?RgH+5HSkPnoKH0SJWe6czHcg8TKO2Gs6lSHP?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 08:44:54.1469 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b60df655-ed4f-40a6-8592-08ddaf0d900d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7711 This patch series adds support for NVIDIA's Voltage Regulator Specification (VRS) Power Sequencer (PSEQ) controller. This controller includes a PSEQ hardware block, that manages power sequencing and voltage regulation for various components in the system. This controller also provides 32kHz RTC support with backup battery for system timing. The series includes: - Device tree bindings for the VRS PSEQ controller - MFD driver to handle the core functionality - RTC driver for the PSEQ's real-time clock functionality - Device tree nodes for Tegra234 platforms - Configuration updates to enable the driver - driver entry in MAINTAINERS Changes in v4: - fixed device tree node name to "pmic@3c" in dtb aliases Changes in v3: - fixed device tree node name to generic "pmic@3c" - fixed indentation in dt-bindings - added rate limiting to interrupt clearing debug logs - removed unnecessary braces in if blocks - changed dependency from I2C=y to I2C in mfd Kconfig - fixed return value in RTC driver function calls - fixed sizeof(*variable) inside rtc driver devm_kzalloc - switch to devm_device_init_wakeup() for automatic cleanup Changes in v2: - fixed, copyrights, definitions and dtb node in dt-bindings - removed unnecessary logs from MFD and RTC driver - fixed RTC allocation and registration APIs - removed unnecessary functions in RTC driver - used rtc_lock/unlock in RTC irq handler - added alias to assign VRS RTC as RTC0 - added driver entry in MAINTAINERS - few other miinor changes done in drivers Shubhi Garg (6): dt-bindings: mfd: add NVIDIA VRS PSEQ arm64: tegra: Add device-tree node for NVVRS PSEQ mfd: nvvrs: add NVVRS PSEQ MFD driver rtc: nvvrs: add NVIDIA VRS PSEQ RTC device driver arm64: defconfig: enable NVIDIA VRS PSEQ MAINTAINERS: Add NVIDIA VRS PSEQ driver entry .../bindings/mfd/nvidia,vrs-pseq.yaml | 60 +++ MAINTAINERS | 9 + .../arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 11 + .../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 15 + arch/arm64/configs/defconfig | 2 + drivers/mfd/Kconfig | 12 + drivers/mfd/Makefile | 1 + drivers/mfd/nvidia-vrs-pseq.c | 267 ++++++++++ drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-nvidia-vrs-pseq.c | 457 ++++++++++++++++++ include/linux/mfd/nvidia-vrs-pseq.h | 127 +++++ 12 files changed, 972 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/nvidia,vrs-pseq.yaml create mode 100644 drivers/mfd/nvidia-vrs-pseq.c create mode 100644 drivers/rtc/rtc-nvidia-vrs-pseq.c create mode 100644 include/linux/mfd/nvidia-vrs-pseq.h -- 2.43.0