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Sun, 3 Aug 2025 21:17:04 -0700 From: Prathamesh Shete To: , , , , , , , , , , CC: Subject: [PATCH 2/2] gpio: tegra186: Add support for Tegra256 Date: Mon, 4 Aug 2025 09:46:57 +0530 Message-ID: <20250804041657.27688-2-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250804041657.27688-1-pshete@nvidia.com> References: <20250804041657.27688-1-pshete@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|MN2PR12MB4109:EE_ X-MS-Office365-Filtering-Correlation-Id: e10e1a76-8d1c-4aa5-7d33-08ddd30dc8c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/SQlaf/kUHldfTcVoRMU+BhXnXAEY839/TqmDJpBeyrUuK0lpjvTLSwM0QIY?= =?us-ascii?Q?Y1anZThi75a2xSt79BCnCavh2io4TJTsSaASLVS3cnl/Fz+dMx6K5H0GaL2Q?= =?us-ascii?Q?F7d4ODkTnrRz7ZWoz0Hft+bGXJDjLjpbJ48Ks8c3vUEwph2DtfdeS1O6J7kb?= =?us-ascii?Q?RE01gFqEurQTzsvAM0wB8rL20XNP2RiqJDKZmQd6n1H/ljkFTqvQPMXtdIrc?= =?us-ascii?Q?W/4jcyVpK4f+l+kSZ9K+O7/mwWok6KhCy5nOMhHi5HoJL4V7d+NKQOA1miSJ?= =?us-ascii?Q?bVZm0KBEaPrVFiToJ0FIk6AxB8wH5csayf9m1IU36Ac1rN3i/68hX5YFMnP4?= =?us-ascii?Q?9rwlMAPBISlEGH5m/ZsC/a1rxizHV3pP7GeGnBWRQeJtbOJKogYicMOEYTTQ?= =?us-ascii?Q?KnWKCCw83CUgLRb9Hj7UOR9e1lQLqeQPzG11LM2nHrxcoNHa7cMXpbbHuMd2?= =?us-ascii?Q?BBAywKz4mVhhxbMFPDUfaDcd+ZR3SL+UlnYKkH0trXM+HCHFsJUhCPTkbMz0?= =?us-ascii?Q?ZR8bSDYIQ7s5WgzRxu4nwCl5R/JEKlM5aN9cx/JmJ3YpD36rd3gfJBIPzjDz?= =?us-ascii?Q?pxnhwx8JSKYSBQmRBkI9oouuDPlI+/z26lDfgdM1FUQlLtQxzv5VDGcSofYW?= =?us-ascii?Q?6cv5PldSt92sHCP2s810M6QQqy4DkWEKgvRMiSpeRtG5GVKjuYYqzDMkD9YC?= =?us-ascii?Q?H6hfgGCCs6ABgxm4BE6LJjzWfWk2jLykpQqfOiVWA5K0B/OKLGqYRxPYBDZW?= =?us-ascii?Q?gWStdm8eQZsbLKErcf02TpHuRGnQRxreTUU4v/7FPwWcjks4ZNldXYp3V+5X?= =?us-ascii?Q?FLXpaF/3ITFTSZbyqUgH0AdyKafBjeHdzcDhgpopTPwMofOYp2+oEcFnubRH?= =?us-ascii?Q?2s7v9Mcq6yBXbFwXhFcn42DAWK0SykpI1p/ZU6OWTswkIBGAuxim0lvsEecI?= =?us-ascii?Q?SDkSsLPJJhleMwJFwSxvDDDgOfNElSFS6/EAjrG0OKKI/kR7FsR6gLFF6swe?= =?us-ascii?Q?jM9BOZSGC76LKNm4Ye1zLNTbGEG02w1GRlb3eB4dbJyTEFZdCyFdjo4ylNuA?= =?us-ascii?Q?ftzskQPRHmrGmyLYYlkJT/ekTqUDMyNL8j7hhizRAiyaZIvPf1F6Xx+bgrtX?= =?us-ascii?Q?uV1KbsesJ5MwYa5cSFjvO4RxN1hWPlsfdoORVRzGl3mHs0K7EjCHH5FPS6QZ?= =?us-ascii?Q?kYdTJgYmurL4IX1w1jgcdu4oR2NtPkxuFv9m9vpRoHAMAYdApU75DVF840M/?= =?us-ascii?Q?f+5JEVoWkoSM6P8bLrBlnm0IcroWp/uwlqn9VtD2qEZ+9Y07rSBip8FvnLW5?= =?us-ascii?Q?1Ulf57r9zp+9rHbz7ykR38CQ96nMrFK0tRwTjugjkNMd0/Y3aDL5CU8xGrGN?= =?us-ascii?Q?1JrBr1tCniG6taCmHaNqqQXjQlgOnResJW/L8Wa696OzPpa9UVhEiEqPPMsc?= =?us-ascii?Q?1YHf5OFlknrVcpj5Y1arDTPSd4h8BfqBWMTB+h86u4+Eu7AVZQeCFxGFMvp0?= =?us-ascii?Q?ZD3yI/Pq9HrysDfNXZCrLyjr8zCrNOiXIdyHFEhF9nT5nWbmGCcgDzCPyg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 04:17:11.1600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e10e1a76-8d1c-4aa5-7d33-08ddd30dc8c0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4109 Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra256. While the programming model remains the same, the number of pins has slightly changed. Signed-off-by: Prathamesh Shete --- drivers/gpio/gpio-tegra186.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d27bfac6c9f5..c9f1441a7b30 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -20,6 +20,7 @@ #include #include #include +#include /* security registers */ #define TEGRA186_GPIO_CTL_SCR 0x0c @@ -1274,6 +1275,30 @@ static const struct tegra_gpio_soc tegra241_aon_soc = { .has_vm_support = false, }; +#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ + [TEGRA256_MAIN_GPIO_PORT_##_name] = { \ + .name = #_name, \ + .bank = _bank, \ + .port = _port, \ + .pins = _pins, \ + } + +static const struct tegra_gpio_port tegra256_main_ports[] = { + TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), + TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), + TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), + TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), +}; + +static const struct tegra_gpio_soc tegra256_main_soc = { + .num_ports = ARRAY_SIZE(tegra256_main_ports), + .ports = tegra256_main_ports, + .name = "tegra256-gpio-main", + .instance = 1, + .num_irqs_per_bank = 8, + .has_vm_support = true, +}; + static const struct of_device_id tegra186_gpio_of_match[] = { { .compatible = "nvidia,tegra186-gpio", @@ -1293,6 +1318,9 @@ static const struct of_device_id tegra186_gpio_of_match[] = { }, { .compatible = "nvidia,tegra234-gpio-aon", .data = &tegra234_aon_soc + }, { + .compatible = "nvidia,tegra256-gpio", + .data = &tegra256_main_soc }, { /* sentinel */ } -- 2.17.1