Re: [PATCH v3 6/6] ARM: tegra: Add SOCTHERM support on Tegra114

Mikko Perttunen
2025-08-21T07:45:50Z

On Wednesday, August 20, 2025 8:42 PM Svyatoslav Ryhel wrote:
> Add SOCTHERM and thermal zones nodes into common Tegra 4 device tree.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> arch/arm/boot/dts/nvidia/tegra114.dtsi | 197 +++++++++++++++++++++++++
> 1 file changed, 197 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 3ee51d7f3935..d9c51e6900d8
> 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -5,6 +5,7 @@
> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/tegra114-car.h>
> +#include <dt-bindings/thermal/tegra114-soctherm.h>

't'hermal comes after 's'oc

> #include <dt-bindings/soc/tegra-pmc.h>
>
> / {
> @@ -694,6 +695,46 @@ mipi: mipi@700e3000 {
> #nvidia,mipi-calibrate-cells = <1>;
> };
>
> + soctherm: thermal-sensor@700e2000 {
> + compatible = "nvidia,tegra114-soctherm";
> + reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
> + <0x60006000 0x400>; /* CAR reg_base */

Regrettable that the binding has CAR registers here, but that's a pre-existing
problem and not something we need to fix here.

> + reg-names = "soctherm-reg", "car-reg";

Same for these names..

> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "thermal", "edp";
> + clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
> + <&tegra_car TEGRA114_CLK_SOC_THERM>;
> + clock-names = "tsensor", "soctherm";
> + resets = <&tegra_car 78>;
> + reset-names = "soctherm";
> +
> + assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
> + <&tegra_car TEGRA114_CLK_SOC_THERM>;
> + assigned-clock-rates = <500000>, <51000000>;
> +
> + assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>,
> + <&tegra_car TEGRA114_CLK_PLL_P>;
> +
> + #thermal-sensor-cells = <1>;
> +
> + throttle-cfgs {
> + throttle_heavy: heavy {
> + nvidia,priority = <100>;
> + nvidia,cpu-throt-percent = <80>;
> + nvidia,gpu-throt-level =
<TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

As mentioned elsewhere, these should have TEGRA114 prefixes.

> + #cooling-cells = <2>;
> + };
> +
> + throttle_light: light {
> + nvidia,priority = <80>;
> + nvidia,cpu-throt-percent = <50>;
> + nvidia,gpu-throt-level =
<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
> + #cooling-cells = <2>;
> + };
> + };
> + };
> +
> dfll: clock@70110000 {
> compatible = "nvidia,tegra114-dfll";
> reg = <0x70110000 0x100>, /* DFLL control */
> @@ -858,24 +899,28 @@ cpu0: cpu@0 {
> clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
"dfll";
> /* FIXME: what's the actual transition time? */
> clock-latency = <300000>;
> + #cooling-cells = <2>;
> };
>
> cpu1: cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <1>;
> + #cooling-cells = <2>;
> };
>
> cpu2: cpu@2 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <2>;
> + #cooling-cells = <2>;
> };
>
> cpu3: cpu@3 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <3>;
> + #cooling-cells = <2>;
> };
> };
>
> @@ -888,6 +933,158 @@ pmu {
> interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> };
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors =
> + <&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>;
> +
> + trips {
> + cpu-shutdown-trip {
> + temperature = <102000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> +
> + cpu_throttle_trip: cpu-throttle-trip {
> + temperature = <100000>;
> + hysteresis = <1000>;
> + type = "hot";
> + };
> +
> + cpu_balanced_trip: cpu-balanced-trip {
> + temperature = <90000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_throttle_trip>;
> + cooling-device = <&throttle_heavy
1 1>;
> + };
> +
> + map1 {
> + trip = <&cpu_balanced_trip>;
> + cooling-device = <&throttle_light
1 1>;
> + };
> + };
> + };
> +
> + mem-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors =
> + <&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>;
> +
> + trips {
> + mem-shutdown-trip {
> + temperature = <102000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> +
> + mem_throttle_trip: mem-throttle-trip {
> + temperature = <100000>;
> + hysteresis = <1000>;
> + type = "hot";
> + };
> +
> + mem_balanced_trip: mem-balanced-trip {
> + temperature = <90000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + /*
> + * There are currently no cooling maps,
> + * because there are no cooling devices.
> + */
> + };
> + };
> +
> + gpu-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors =
> + <&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>;
> +
> + trips {
> + gpu-shutdown-trip {
> + temperature = <102000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> +
> + gpu_throttle_trip: gpu-throttle-trip {
> + temperature = <100000>;
> + hysteresis = <1000>;
> + type = "hot";
> + };
> +
> + gpu_balanced_trip: gpu-balanced-trip {
> + temperature = <90000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&gpu_throttle_trip>;
> + cooling-device = <&throttle_heavy
1 1>;
> + };
> +
> + map1 {
> + trip = <&gpu_balanced_trip>;
> + cooling-device = <&throttle_light
1 1>;
> + };
> + };
> + };
> +
> + pllx-thermal {
> + polling-delay-passive = <1000>;
> + polling-delay = <1000>;
> +
> + thermal-sensors =
> + <&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>;
> +
> + trips {
> + pllx-shutdown-trip {
> + temperature = <102000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> +
> + pllx_throttle_trip: pllx-throttle-trip {
> + temperature = <100000>;
> + hysteresis = <1000>;
> + type = "hot";
> + };
> +
> + pllx_balanced_trip: pllx-balanced-trip {
> + temperature = <90000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };
> + };
> +
> + cooling-maps {
> + /*
> + * There are currently no cooling maps,
> + * because there are no cooling devices.
> + */
> + };
> + };
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts =