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Fri, 22 Aug 2025 22:54:22 -0700 From: Prathamesh Shete To: , , , , , , , , , , CC: Subject: [PATCH 1/2] dt-bindings: gpio: Add Tegra256 support Date: Sat, 23 Aug 2025 11:24:19 +0530 Message-ID: <20250823055420.24664-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DA:EE_|SA1PR12MB7366:EE_ X-MS-Office365-Filtering-Correlation-Id: ba7c46cd-2c69-491f-4ca0-08dde20989c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?R4gbPyCHlPPFHCP8hm662jMz0x0UIZlWX0mXJyubA7ypgZ/uE4W+pGewMQk4?= =?us-ascii?Q?jR2cY/qGqdHOEcG5xhpSxZ8MpKCsvGsTZ7FFtxBFLs0VvWyM8baZITJzYkSC?= =?us-ascii?Q?ReBz6kM901t/6a6+tZtXL2dSwgjm6nFMc3HR/sy5U31hPOxu3rnNKcol+bpO?= =?us-ascii?Q?YJiWONrCJAyMCexl+f2lXwGTwgcwctqKTxqW3hjFAQT8aATWYzwn+1hShEIx?= =?us-ascii?Q?hltvYNNxnChv3PAN+c/jMFQ/MjvXyHdVhym+E012GF9k1M3YiceuKvLIXm2n?= =?us-ascii?Q?+ny6xxHcituT1ry/LOHQ2R2/11SHlsgIBuueJFpSAxfXLHKC77U2hLvBs7NH?= =?us-ascii?Q?KjoZWyrSU5ja9KntkEsURRz7M+04/T/ea2EgGKYiY1uannV473SEHYzcUb7q?= =?us-ascii?Q?IteK0qnOkJ/ZQauENWH/Cp0VBX7By0U0DXpT9gktca8dF0+6okB4G/Orp9eb?= =?us-ascii?Q?6UXq61T93bihdqt5a3SgzNlxB3Myw2BgvmIGMU9P89OhckB0Wi6wd2rcyw1Q?= =?us-ascii?Q?hHQcKCuldIvORbzxzs6o3BYO72sYPH/n/2HSRFwvB8JmhjFiMIm4eoJdtmGg?= =?us-ascii?Q?iUx23pPVqSUW2uzBCYkq6TYG5UBQ2JUH1XHTxDiySHYn0U+awPpcxJTQXs4k?= =?us-ascii?Q?lqrEmvRKfBttHwgSG8+vDehgsoi+k6dfXHxDCPQWq12RJrjsENkiHf0Ieur0?= =?us-ascii?Q?3PcCMpNjULaWvNYOHHqFt666NgtQ7kGuAdV+wcAR0lwXsRrngsCcoS2C4lKW?= =?us-ascii?Q?1tzZP0kr+b5PBS7srq6j+QoK7DiaJb6RcqqQA31mZ2lut2cG0/CDKOCcz/Th?= =?us-ascii?Q?cq9IN+EDB6vS55D5w5+hB6+mSCtdeSZ4w8Kq1E1yMT0KKZ1ZF5vK7tM5jyiG?= =?us-ascii?Q?6OzUMe05OkdWzuXhs5GLl7DKZ7zwfMRvvtWOXvKfZJ12r9ijwh9cyBTLyUO7?= =?us-ascii?Q?pwUKbiNmAc1kVOobkjfW0U+M8VMKzmlpq2r/Bwv8lKSLt8E6oX9t+0o9SK/R?= =?us-ascii?Q?LZwjcJA1vRV0OZMynPI43ZNuXxihf3kwm8WSx35UBPpsgFBnY9dS0TibaEuk?= =?us-ascii?Q?g5TX1Ei6YmRDY4XZJ9COK/F+ppeKO99wdUPbc9xn4Kt93YCsxIYp7C6KJX/p?= =?us-ascii?Q?yNgwyUdNtpayWFiVxmP6Es87OCmVuOA7JEUc8B+0NNMPBozT++K6SWelMnnH?= =?us-ascii?Q?+LrjAHrd09jal1Ll0umdU7lx+RGnOkrchB5K2f7UC3MBjJzU2opqceNJel6e?= =?us-ascii?Q?48VYjz29watJGRf0jHeBkoY3Yxpvuf/igMQNX/nT7d66wVsBf7G+j+pVZYYr?= =?us-ascii?Q?yVCzdu3yJngPylKkv+/QcXiv4xF5AuaEkhIj6Pf5I2KfqehKwlrMGucz95If?= =?us-ascii?Q?ix58r0r6aTtWjIWkuG3Rl8Xwpw8U9+OrsIo71TP8o1d7lZqfLTERA1n7/B4O?= =?us-ascii?Q?/Nkj2VTr+u+gewHg2OzwLzYF7v8E3y51GCQDJvLjlA2kVAqdTC6PbUcDTr6E?= =?us-ascii?Q?vsOXTcE0JYjuJRSGNAER0+COTq6J7ePrlLpNXeXNPgyBwwQalb9EDTFvTg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2025 05:54:34.8884 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba7c46cd-2c69-491f-4ca0-08dde20989c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7366 Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra256. The number of pins is slightly different, but the programming model remains the same Add a new header, include/dt-bindings/gpio/tegra256-gpio.h, that defines port IDs as well as the TEGRA256_MAIN_GPIO() helper, both of which are used in conjunction to create a unique specifier for each pin. The OS can reconstruct the port ID and pin from these values to determine the register region for the corresponding GPIO. However, the OS does not use the macro definitions in this file. The symbolic names help associate these GPIO specifiers with the names used in the technical documentation available for the chip. Signed-off-by: Prathamesh Shete --- .../bindings/gpio/nvidia,tegra186-gpio.yaml | 2 ++ include/dt-bindings/gpio/tegra256-gpio.h | 28 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 include/dt-bindings/gpio/tegra256-gpio.h diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 065f5761a93f..2bd620a1099b 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,7 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra256-gpio reg-names: items: @@ -155,6 +156,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra256-gpio then: properties: interrupts: diff --git a/include/dt-bindings/gpio/tegra256-gpio.h b/include/dt-bindings/gpio/tegra256-gpio.h new file mode 100644 index 000000000000..a0353a302aeb --- /dev/null +++ b/include/dt-bindings/gpio/tegra256-gpio.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ + +/* + * This header provides constants for the nvidia,tegra256-gpio DT binding. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. + * The macros below provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H +#define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H + +#include + +/* GPIOs implemented by main GPIO controller */ +#define TEGRA256_MAIN_GPIO_PORT_A 0 +#define TEGRA256_MAIN_GPIO_PORT_B 1 +#define TEGRA256_MAIN_GPIO_PORT_C 2 +#define TEGRA256_MAIN_GPIO_PORT_D 3 + +#define TEGRA256_MAIN_GPIO(port, offset) \ + ((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset)) + +#endif + -- 2.17.1