From: Svyatoslav Ryhel <clamor95@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Thierry Reding" <treding@nvidia.com>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Sowjanya Komatineni" <skomatineni@nvidia.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Svyatoslav Ryhel" <clamor95@gmail.com>,
"Dmitry Osipenko" <digetx@gmail.com>,
"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
"Charan Pedumuru" <charan.pedumuru@gmail.com>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
linux-staging@lists.linux.dev
Subject: [PATCH v2 19/23] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16
Date: Sat, 6 Sep 2025 16:53:40 +0300 [thread overview]
Message-ID: <20250906135345.241229-20-clamor95@gmail.com> (raw)
In-Reply-To: <20250906135345.241229-1-clamor95@gmail.com>
Add support for Bayer formats (RAW8 and RAW10) and YUV422_8 1X16 versions
of existing YUV422_8 2X8.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/staging/media/tegra-video/tegra20.c | 72 ++++++++++++++++++++-
1 file changed, 69 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
index 3c5bafebfcd8..f9adb0611638 100644
--- a/drivers/staging/media/tegra-video/tegra20.c
+++ b/drivers/staging/media/tegra-video/tegra20.c
@@ -187,6 +187,18 @@ static void tegra20_vi_get_input_formats(struct tegra_vi_channel *chan,
case MEDIA_BUS_FMT_YVYU8_2X8:
(*yuv_input_format) = VI_INPUT_YUV_INPUT_FORMAT_YVYU;
break;
+ /* RAW8 */
+ case MEDIA_BUS_FMT_SBGGR8_1X8:
+ case MEDIA_BUS_FMT_SGBRG8_1X8:
+ case MEDIA_BUS_FMT_SGRBG8_1X8:
+ case MEDIA_BUS_FMT_SRGGB8_1X8:
+ /* RAW10 */
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ (*main_input_format) = VI_INPUT_INPUT_FORMAT_BAYER;
+ break;
}
}
@@ -221,6 +233,18 @@ static void tegra20_vi_get_output_formats(struct tegra_vi_channel *chan,
case V4L2_PIX_FMT_YVU420:
(*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR;
break;
+ /* RAW8 */
+ case V4L2_PIX_FMT_SBGGR8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SRGGB8:
+ /* RAW10 */
+ case V4L2_PIX_FMT_SBGGR10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SRGGB10:
+ (*main_output_format) = VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT;
+ break;
}
}
@@ -301,6 +325,16 @@ static void tegra20_channel_queue_setup(struct tegra_vi_channel *chan)
case V4L2_PIX_FMT_VYUY:
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_YVYU:
+ /* RAW8 */
+ case V4L2_PIX_FMT_SRGGB8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SBGGR8:
+ /* RAW10 */
+ case V4L2_PIX_FMT_SRGGB10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SBGGR10:
if (chan->vflip)
chan->start_offset += stride * (height - 1);
if (chan->hflip)
@@ -366,6 +400,19 @@ static void tegra20_channel_vi_buffer_setup(struct tegra_vi_channel *chan,
tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(TEGRA_VI_OUT_1), base);
tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(TEGRA_VI_OUT_1), base + chan->start_offset);
break;
+ /* RAW8 */
+ case V4L2_PIX_FMT_SRGGB8:
+ case V4L2_PIX_FMT_SGRBG8:
+ case V4L2_PIX_FMT_SGBRG8:
+ case V4L2_PIX_FMT_SBGGR8:
+ /* RAW10 */
+ case V4L2_PIX_FMT_SRGGB10:
+ case V4L2_PIX_FMT_SGRBG10:
+ case V4L2_PIX_FMT_SGBRG10:
+ case V4L2_PIX_FMT_SBGGR10:
+ tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(TEGRA_VI_OUT_2), base);
+ tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(TEGRA_VI_OUT_2), base + chan->start_offset);
+ break;
}
}
@@ -447,12 +494,15 @@ static int tegra20_chan_capture_kthread_start(void *data)
static void tegra20_camera_capture_setup(struct tegra_vi_channel *chan)
{
u32 output_fourcc = chan->format.pixelformat;
+ u32 data_type = chan->fmtinfo->img_dt;
int width = chan->format.width;
int height = chan->format.height;
int stride_l = chan->format.bytesperline;
int stride_c = (output_fourcc == V4L2_PIX_FMT_YUV420 ||
output_fourcc == V4L2_PIX_FMT_YVU420) ? 1 : 0;
- enum tegra_vi_out output_channel = TEGRA_VI_OUT_1;
+ enum tegra_vi_out output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 ||
+ data_type == TEGRA_IMAGE_DT_RAW10) ?
+ TEGRA_VI_OUT_2 : TEGRA_VI_OUT_1;
int main_output_format;
int yuv_output_format;
@@ -581,6 +631,20 @@ static const struct tegra_video_format tegra20_video_formats[] = {
TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YVYU),
TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420),
TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420),
+ TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 16, UYVY),
+ TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 16, VYUY),
+ TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 16, YUYV),
+ TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 16, YVYU),
+ /* RAW 8 */
+ TEGRA20_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 16, SRGGB8),
+ TEGRA20_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 16, SGRBG8),
+ TEGRA20_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 16, SGBRG8),
+ TEGRA20_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 16, SBGGR8),
+ /* RAW 10 */
+ TEGRA20_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 16, SRGGB10),
+ TEGRA20_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 16, SGRBG10),
+ TEGRA20_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 16, SGBRG10),
+ TEGRA20_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 16, SBGGR10),
};
const struct tegra_vi_soc tegra20_vi_soc = {
@@ -607,10 +671,12 @@ const struct tegra_vi_soc tegra20_vi_soc = {
static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan)
{
struct tegra_vi_channel *vi_chan = v4l2_get_subdev_hostdata(&vip_chan->subdev);
+ u32 data_type = vi_chan->fmtinfo->img_dt;
int width = vi_chan->format.width;
int height = vi_chan->format.height;
- enum tegra_vi_out output_channel = TEGRA_VI_OUT_1;
-
+ enum tegra_vi_out output_channel = (data_type == TEGRA_IMAGE_DT_RAW8 ||
+ data_type == TEGRA_IMAGE_DT_RAW10) ?
+ TEGRA_VI_OUT_2 : TEGRA_VI_OUT_1;
unsigned int main_input_format;
unsigned int yuv_input_format;
--
2.48.1
next prev parent reply other threads:[~2025-09-06 13:54 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-06 13:53 [PATCH v2 00/23] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 01/23] clk: tegra: set CSUS as vi_sensors gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-09-19 6:29 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 02/23] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-07 9:34 ` Krzysztof Kozlowski
2025-09-07 9:43 ` Svyatoslav Ryhel
2025-09-07 18:25 ` Krzysztof Kozlowski
2025-09-06 13:53 ` [PATCH v2 03/23] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-19 6:33 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 04/23] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-09-06 19:17 ` Rob Herring (Arm)
2025-09-06 13:53 ` [PATCH v2 05/23] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-17 7:52 ` Luca Ceresoli
2025-09-06 13:53 ` [PATCH v2 06/23] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 07/23] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 08/23] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 09/23] gpu: host1x: convert MIPI to use operations Svyatoslav Ryhel
2025-09-19 6:47 ` Mikko Perttunen
2025-09-19 7:58 ` Svyatoslav Ryhel
2025-09-19 8:56 ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 10/23] staging: media: tegra-video: csi: add support for SoCs with integrated MIPI calibration Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 11/23] staging: media: tegra-video: csi: add a check to tegra_channel_get_remote_csi_subdev Svyatoslav Ryhel
2025-09-16 16:04 ` Luca Ceresoli
2025-09-16 16:24 ` Svyatoslav Ryhel
2025-09-17 7:25 ` Luca Ceresoli
2025-09-17 7:49 ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 12/23] dt-bindings: display: tegra: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-09 0:49 ` Rob Herring (Arm)
2025-09-09 0:57 ` Rob Herring
2025-09-09 5:00 ` Svyatoslav Ryhel
2025-09-09 16:03 ` Rob Herring
2025-09-06 13:53 ` [PATCH v2 13/23] staging: media: tegra-video: csi: " Svyatoslav Ryhel
2025-09-17 7:52 ` Luca Ceresoli
2025-09-22 4:11 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 14/23] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 15/23] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-22 4:29 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 16/23] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-09-22 4:44 ` Mikko Perttunen
2025-09-22 5:13 ` Svyatoslav Ryhel
2025-09-22 6:23 ` Mikko Perttunen
2025-09-22 6:30 ` Svyatoslav Ryhel
2025-09-22 7:27 ` Mikko Perttunen
2025-09-22 7:36 ` Svyatoslav Ryhel
2025-09-23 6:03 ` Mikko Perttunen
2025-09-23 6:11 ` Svyatoslav Ryhel
2025-09-23 6:50 ` Svyatoslav Ryhel
2025-09-24 4:47 ` Mikko Perttunen
2025-09-24 10:24 ` Svyatoslav Ryhel
2025-09-24 23:20 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 17/23] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-22 4:54 ` Mikko Perttunen
2025-09-22 4:58 ` Svyatoslav Ryhel
2025-09-22 6:23 ` Mikko Perttunen
2025-09-06 13:53 ` Svyatoslav Ryhel [this message]
2025-09-22 5:00 ` [PATCH v2 19/23] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 20/23] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-09-09 16:26 ` Rob Herring
2025-09-09 16:39 ` Svyatoslav Ryhel
2025-09-10 2:13 ` Rob Herring
2025-09-06 13:53 ` [PATCH v2 22/23] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 23/23] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-15 5:46 ` kernel test robot
2025-09-22 5:15 ` Mikko Perttunen
2025-09-22 5:19 ` Svyatoslav Ryhel
2025-09-22 5:38 ` Mikko Perttunen
2025-09-22 6:16 ` Svyatoslav Ryhel
2025-09-22 6:36 ` Mikko Perttunen
2025-09-11 16:03 ` (subset) [PATCH v2 00/23] " Thierry Reding
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