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[2003:e4:1f27:4600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429dc1a850fsm4828168f8f.20.2025.11.04.05.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 05:23:49 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: sheetal , linux-tegra@vger.kernel.org Subject: [PATCH] arm64: tegra: Move HDA into the correct bus Date: Tue, 4 Nov 2025 14:23:45 +0100 Message-ID: <20251104132345.1689397-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.51.2 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Thierry Reding HDA is part of the DISP_USB bus, so move it into that and drop the address prefix accordingly. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra264-p3971.dtsi | 4 ++- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 32 +++++++++---------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi index 1fcfac2066ae..b1bd4ee7aee3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi @@ -29,8 +29,10 @@ interrupt-controller@9960000 { status = "okay"; }; }; + }; - hda@88090b0000 { + bus@8800000000 { + hda@90b0000 { nvidia,model = "NVIDIA Jetson Thor AGX HDA"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index c66ea12ef5a3..f137565da804 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3347,22 +3347,6 @@ pmc: pmc@c800000 { #interrupt-cells = <2>; interrupt-controller; }; - - hda@88090b0000 { - compatible = "nvidia,tegra264-hda"; - reg = <0x88 0x90b0000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; - clock-names = "hda"; - resets = <&bpmp TEGRA264_RESET_HDA>, - <&bpmp TEGRA264_RESET_HDACODEC>; - reset-names = "hda", "hda2codec_2x"; - interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, - <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu3 TEGRA264_SID_HDA>; - status = "disabled"; - }; }; /* TOP_MMIO */ @@ -3716,6 +3700,22 @@ smmu3: iommu@6000000 { #iommu-cells = <1>; dma-coherent; }; + + hda@90b0000 { + compatible = "nvidia,tegra264-hda"; + reg = <0x0 0x90b0000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names = "hda"; + resets = <&bpmp TEGRA264_RESET_HDA>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu3 TEGRA264_SID_HDA>; + status = "disabled"; + }; }; /* UPHY MMIO */ -- 2.51.2