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[2003:e4:1f27:4600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6411f713aa2sm21117a12.1.2025.11.05.11.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Nov 2025 11:53:47 -0800 (PST) From: Thierry Reding To: Thierry Reding , Krzysztof Kozlowski Cc: Rob Herring , Conor Dooley , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/3] memory: tegra: Add support for DBB clock on Tegra264 Date: Wed, 5 Nov 2025 20:53:41 +0100 Message-ID: <20251105195342.2705855-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251105195342.2705855-1-thierry.reding@gmail.com> References: <20251105195342.2705855-1-thierry.reding@gmail.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Thierry Reding The DBB clock is needed by many IP blocks in order to access system memory via the data backbone. The memory controller and external memory controllers are the central place where these accesses are managed, so make sure that the clock can be controlled from the corresponding driver. Note that not all drivers fully register bandwidth requests, and hence the EMC driver doesn't have enough information to know when it's safe to switch the clock off, so for now it will be kept on permanently. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186-emc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 74be09968baa..7a26d8830172 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -33,6 +33,7 @@ struct tegra186_emc { struct tegra_bpmp *bpmp; struct device *dev; struct clk *clk; + struct clk *clk_dbb; struct tegra186_emc_dvfs *dvfs; unsigned int num_dvfs; @@ -452,6 +453,13 @@ static int tegra186_emc_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(emc->clk), "failed to get EMC clock\n"); + emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb"); + if (IS_ERR(emc->clk_dbb)) { + err = PTR_ERR(emc->clk_dbb); + dev_err(&pdev->dev, "failed to get DBB clock: %d\n", err); + goto put_bpmp; + } + platform_set_drvdata(pdev, emc); emc->dev = &pdev->dev; -- 2.51.2