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Sun, 11 Jan 2026 20:28:53 -0800 From: "Sheetal ." To: Mark Brown CC: Sander Vanheule , Greg Kroah-Hartman , "Rafael J . Wysocki" , Danilo Krummrich , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "Thierry Reding" , Jonathan Hunter , Mohan kumar , , , , Sheetal Subject: [RFC PATCH v2 0/3] regmap: Add flat_cache_default_is_zero flag for flat cache Date: Mon, 12 Jan 2026 09:58:38 +0530 Message-ID: <20260112042841.51799-1-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|MN2PR12MB4341:EE_ X-MS-Office365-Filtering-Correlation-Id: 326988c9-38ef-42b9-033f-08de51932444 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Q1QwlVK2pA1dQCXoCL/K349XcZ6b+2zKh2cO7avGRFQlzboidhhdhq3fyX1c?= =?us-ascii?Q?1wz9Tk4TzxXzsJvG6pgumR0cATHK5MNtLpIb+4aFa+1NeOTZ+ns2FkN+7rch?= =?us-ascii?Q?bnWZ225KmxhR+9eGlmE8PdeC028HBq0qwuIXzT4zcyEYWEGQ+69LKkekFUR5?= =?us-ascii?Q?6qTwQZime1qUZKvlag0lNGFHpk9ug6WnBzvjcfX3zhBDd5zt+0wpDL6nk7M/?= =?us-ascii?Q?eCyDDAgEA4LMTbQYpWwgnxz3+MIxmHmCRAzCWp5SJTlp+JdrxQ6y8LODXq9F?= =?us-ascii?Q?KxmzEAT0TenNxhu6gnkvN7ftcUszO64yeX6FSgB5CLs9gYEr3c3zSU4DxvFj?= =?us-ascii?Q?OfXWnzhVYgyLSH8GDNQr3dKUrqti9uhD/+d6AQJdfsqw6TzLb6AmoLveN5Re?= =?us-ascii?Q?4PC4imNmqJUTZLcqSRRJaW1DffDvShmMk8dfxELqSf8hh0XTP96gw/zAV0DY?= =?us-ascii?Q?NqlRw3c5Nhx4jEDD+sob0qpfnNgB2H5VyD0syjGoNSmpwaCrESxjpRw6JNGV?= =?us-ascii?Q?6IPZyCZtVV+KRPAYgLoEMGsblmk4Gp9TdmGLwEx/vdomKV/1ys65XBMwwnzs?= =?us-ascii?Q?1BCMOBC2YuFwO6I5z6T7JPWE4hWPpv1hmGx4nGXscN7NB3gc0s8qpefMSsbQ?= =?us-ascii?Q?b4xsJPGpXB6TMDIJOQiApDDIUg7RA4YRMJBTcAAR0zVPUkLaj4YcQcpp9qbi?= =?us-ascii?Q?MsQST1i/Z4NUGzRGGIFtwfm9I6rSek9hOriN4oH9uS45mynh9ViS4AHyIOyk?= =?us-ascii?Q?9nFwKl0oi4Tt1Z66hspXU+BoMrMh5wrcEH0XJ4Qil1dSc7nk+nepKUhdRN3N?= =?us-ascii?Q?5MidQ+hP8roo1ZRgMnvfX2HYmCMwCTyeknKdYC7pbDA5EiK+xvF+xAhXNZUq?= =?us-ascii?Q?X5H48Bim3UibgunhkwBFqEFy+I8gSqIIS/dYeRwGDoggsfa+cnHyAltyGbL+?= =?us-ascii?Q?Vq6wJKmLEJ0GsaeOyBkHCCECI/iNNdhgbArDMe5qx1Z+YQAqEtGfg8lb6lDl?= =?us-ascii?Q?x5Ld6+rItZZxOkYm+4MhbMp/AySVUwL3g+OdTObABO0V5OVLTEZMop6SBZNt?= =?us-ascii?Q?gp01b9UD0TblCMDQMm2QI7+HbqF0AGLMP2KqS/LyEkewIPIbgk+s2tmfKjh3?= =?us-ascii?Q?2VovEdsn4+7ztvAyRe84BvmHA4tZNkm7Q06tHIxFLzPLFHXZF35Es1zNejbC?= =?us-ascii?Q?8v/DuofsGcL9IdPymopf4MnsAlxic8rQUG3muDzY+oYv5GyLALTjKyJJ3l+C?= =?us-ascii?Q?UpUoLwpj5EeEMGHkSx1M4c6vqHkZMT8Lwq9EjD3L9T8mhCKbplVzc5kGyvIB?= =?us-ascii?Q?vRr7Hcb0ouwUjzxpnJioVojfjEujK12DuDzf1upwvOzW9VYLXnxntcwfIyWV?= =?us-ascii?Q?7Dx8i+1PVc1Wejz25KmaFWEZoBGBxNaJx4d7MSdgSuARVXkA4uQ1n/E+pMZX?= =?us-ascii?Q?Y6PSoSc06QNVokZcC8BIzqR2lV1XSxgQDC4BbJtyKDgxQr8a8Sumf77dHJBE?= =?us-ascii?Q?dSceJh0rdEIlcKqw3ErLtNT6lcYTIQ+fdWD4imeKMLJmHYoh+/3WzWiyQjpT?= =?us-ascii?Q?3wcNahSjgLBQtucMezI=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2026 04:29:14.2251 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 326988c9-38ef-42b9-033f-08de51932444 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4341 From: Sheetal This patch series adds a flat_cache_default_is_zero flag for REGCACHE_FLAT that marks cache entries as valid on first read. For hardware with zero power-on-reset registers, this avoids the need to add all such registers to reg_defaults (maintenance burden, code bloat, no functional benefit) just to set the validity bits. By setting valid bits on read rather than at init, only accessed registers are marked valid. This keeps regcache_sync scope minimal and avoids writes to unused registers or holes. Changes in v2: - Renamed flag from cache_default_is_zero to flat_cache_default_is_zero to make it explicit that this is specific to REGCACHE_FLAT - Added KUnit test coverage (patch 2/3) - Updated commit message to explain why valid bits are set on first read rather than at init time Sheetal (3): regmap: Add flat_cache_default_is_zero flag for flat cache regmap: Add KUnit test for flat_cache_default_is_zero ASoC: tegra: Enable flat_cache_default_is_zero for audio drivers drivers/base/regmap/internal.h | 2 ++ drivers/base/regmap/regcache-flat.c | 12 ++++++++---- drivers/base/regmap/regcache.c | 1 + drivers/base/regmap/regmap-kunit.c | 93 ++++++++++++++++++++++++++++++ include/linux/regmap.h | 1 + sound/soc/tegra/tegra186_asrc.c | 1 + sound/soc/tegra/tegra186_dspk.c | 1 + sound/soc/tegra/tegra210_admaif.c | 3 +++ sound/soc/tegra/tegra210_adx.c | 2 ++ sound/soc/tegra/tegra210_ahub.c | 3 +++ sound/soc/tegra/tegra210_amx.c | 3 +++ sound/soc/tegra/tegra210_dmic.c | 1 + sound/soc/tegra/tegra210_i2s.c | 2 ++ sound/soc/tegra/tegra210_mbdrc.c | 1 + sound/soc/tegra/tegra210_mixer.c | 1 + sound/soc/tegra/tegra210_mvc.c | 1 + sound/soc/tegra/tegra210_ope.c | 1 + sound/soc/tegra/tegra210_peq.c | 1 + sound/soc/tegra/tegra210_sfc.c | 1 + 19 files changed, 127 insertions(+), 4 deletions(-) -- 2.34.1