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Mon, 02 Feb 2026 00:05:52 -0800 (PST) From: Svyatoslav Ryhel To: Greg Kroah-Hartman , Mikko Perttunen , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-usb@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/4] usb: phy: tegra: parametrize PORTSC1 register offset Date: Mon, 2 Feb 2026 10:05:26 +0200 Message-ID: <20260202080526.23487-5-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260202080526.23487-1-clamor95@gmail.com> References: <20260202080526.23487-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The PORTSC1 register has a different offset in Tegra20 compared to Tegra30+, yet they share a crucial set of registers required for HSIC functionality. Reflect this register offset change in the SoC config. Signed-off-by: Svyatoslav Ryhel --- drivers/usb/phy/phy-tegra-usb.c | 17 ++++++----------- include/linux/usb/tegra_usb_phy.h | 2 ++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index 812d99443180..00443a7beaeb 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -965,17 +965,10 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel_relaxed(val, base + USB_TXFILLTUNING); } - if (phy->soc_config->has_hostpc) { - val = readl_relaxed(base + TEGRA30_USB_PORTSC1); - val &= ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | - TEGRA_USB_PORTSC1_WKCN); - writel_relaxed(val, base + TEGRA30_USB_PORTSC1); - } else { - val = readl_relaxed(base + TEGRA_USB_PORTSC1); - val &= ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | - TEGRA_USB_PORTSC1_WKCN); - writel_relaxed(val, base + TEGRA_USB_PORTSC1); - } + val = readl_relaxed(base + phy->soc_config->portsc1_offset); + val &= ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS | + TEGRA_USB_PORTSC1_WKCN); + writel_relaxed(val, base + phy->soc_config->portsc1_offset); val = tegra_hsic_readl(phy, UHSIC_PADS_CFG0); val &= ~UHSIC_TX_RTUNEN; @@ -1472,6 +1465,7 @@ static const struct tegra_phy_soc_config tegra20_soc_config = { .uhsic_registers_offset = 0, .uhsic_tx_rtune = 0, /* 40 ohm */ .uhsic_pts_value = 0, /* UTMI */ + .portsc1_offset = TEGRA_USB_PORTSC1, }; static const struct tegra_phy_soc_config tegra30_soc_config = { @@ -1483,6 +1477,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = { .uhsic_registers_offset = 0x400, .uhsic_tx_rtune = 8, /* 50 ohm */ .uhsic_pts_value = TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC, + .portsc1_offset = TEGRA30_USB_PORTSC1, }; static const struct of_device_id tegra_usb_phy_id_table[] = { diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index 81d9f22e58b5..57e22aae6247 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -28,6 +28,7 @@ struct gpio_desc; * comparing to Tegra20 by 0x400, since Tegra20 has no UTMIP on PHY2 * uhsic_tx_rtune: fine tuned 50 Ohm termination resistor for NMOS/PMOS driver * uhsic_pts_value: parallel transceiver select enumeration value + * portsc1_offset: register offset of PORTSC1 */ struct tegra_phy_soc_config { @@ -39,6 +40,7 @@ struct tegra_phy_soc_config { u32 uhsic_registers_offset; u32 uhsic_tx_rtune; u32 uhsic_pts_value; + u32 portsc1_offset; }; struct tegra_utmip_config { -- 2.51.0