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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB56.mail.protection.outlook.com (10.167.241.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.16 via Frontend Transport; Tue, 3 Mar 2026 06:56:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 2 Mar 2026 22:56:11 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 2 Mar 2026 22:56:04 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , , , , , , , <18255117159@163.com> CC: , , , Manikanta Maddireddy Subject: [PATCH v7 08/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Date: Tue, 3 Mar 2026 12:24:43 +0530 Message-ID: <20260303065448.2361488-9-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260303065448.2361488-1-mmaddireddy@nvidia.com> References: <20260303065448.2361488-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB56:EE_|SA0PR12MB4384:EE_ X-MS-Office365-Filtering-Correlation-Id: fc3784eb-031a-4f9f-e625-08de78f1fcdb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b8RIpPM8tZ0fP7ZUdG557l68jMn+FwiuUbQne0fHeGfR13mooy1UCS5vfejt+nv9zChSiptcvoo/c8sPmH5dzXGNJN/ZaExa2qFEColSHco+Tzym9EcnDNHWzr4uw3rC+uRDZ0+2D9WNIDMP5X1ZATnII10J+OOJrIQskPm/eA+8ldk18+wgmhEz8b7NTODQ5dRiy9v60uVFz4LnjKVhgTZjyXqmahiylnOoC9Il5qYZEAUi3gLMn+8fNL9VhDt70ayG42BY3zIJly7lj80B4ll5vFZC+0nQ2NNkS7UK7bj18/3oY1USBWO7LPLF/dBHRPLXZbdcnkf4WKaZt4MBUndWB4fSl311v2wmalXruqIuoBQOwlLUaiJ/LbhgdO9GbpLE9kbfMdhme4BCFoOXjv5HV+VazOJB6j5MACcSOm9SzALpCrFa8TxwmUMXSKUf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 06:56:25.6161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc3784eb-031a-4f9f-e625-08de78f1fcdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB56.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4384 From: Vidya Sagar PERST# and CLKREQ# pinctrl settings should be applied for both Root Port and Endpoint mode. Move pinctrl_pm_select_default_state() function call from Root Port specific configuration function to probe(). Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V5 -> V7: None Changes V4 -> V5: Use dev_err_probe() function Changes V1 -> V4: None drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b50229df890e..5b79d3c28ba6 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1598,12 +1598,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - ret = pinctrl_pm_select_default_state(dev); - if (ret < 0) { - dev_err(dev, "Failed to configure sideband pins: %d\n", ret); - goto fail_pm_get_sync; - } - ret = tegra_pcie_init_controller(pcie); if (ret < 0) { dev_err(dev, "Failed to initialize controller: %d\n", ret); @@ -2077,6 +2071,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + ret = pinctrl_pm_select_default_state(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to configure sideband pins: %d\n", ret); + ret = tegra_pcie_dw_parse_dt(pcie); if (ret < 0) { const char *level = KERN_ERR; -- 2.34.1