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Mon, 2 Mar 2026 22:58:19 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , , , , , , , <18255117159@163.com> CC: , , , Manikanta Maddireddy Subject: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly Date: Tue, 3 Mar 2026 12:27:50 +0530 Message-ID: <20260303065758.2364340-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260303065758.2364340-1-mmaddireddy@nvidia.com> References: <20260303065758.2364340-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBB:EE_|LV8PR12MB9451:EE_ X-MS-Office365-Filtering-Correlation-Id: 918d2d1a-24e5-4acb-f1e0-08de78f24c15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: bP4hkrlI8FN/jzjdchYluxD5V1AeGa4ulYp929/pJBwK4Q/1n5waY4kyglefoRV1goV9Os8ta6B2eK7pgyLcMxlG4xsCDtsyZR4XMwMBUSNvHcvfF6FGFHWNe+SH2Cz7ZDoQbuGSsA6hI31HoCd5IhozsstAoAEwDlSE2BbK22sy2YfSKuIDWh96KuOpjZsVwDJjhbSojkemgQOa8dtROlSqiFRDex16D3/sHjivoVPhaN9JPFnrOPa+q7EGoO4WWwikDuvaboLZKeNHmnUegKmoB3zzvVaDs408EekzS4ryx6ZUAgTeck3bYKw7BqX0hOOoldW0cMb7pfGHXJ4nuwVMHjsJPiwhh0ySBpM8mP7WfM7VeNrrumH5b3TixFIPcVtHrpU0yjJ8XTtgttn4yTWv7PVYXLv4LV03beDvAFe9QnCf2uuCp/8GdDkacX51bzkJCgLAeEKn3ipffO2KEHkLbz4PHwhMUMauwiRTJg/Bl27cA+mFrG6+skQF5obbvDWbHm8vZm66zEykhqnsDU61ysKPK/CMmkjE0aMC996tGWZdckB2B759D40Wkq63VHpSIeSXRq1Q0RpVJ/ENAPg2LJGbCfar6UBpHwn1/yc8D7LMpapdipbOYbkxKDAN6qn18smEaIV94jA7Ztvf7VKTMtDdWjTifvyJkpzigFg95BSynUq24sfRCj8BWKm+A4jEuO/LUXg74/L6fLZt/k7KhhQr+SRaa7k9kphi07LvqGedDGwLxYUMriXwMF+3twhUBCFZiIbh/M42AqmY09c+mYtqDRDGYoxBsPT78ZaNTjKW6hJG5hVNm1QvGu1D5ZzfeZ7PWkNp2HxfkLVB2M22HB4yJnrq9hDHJRyceMw= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JkoPI42okptW8aTUIl6Ae4udsWAMeFSULYO8wemp3HJ4KEHZHStUf50qbVeQe58XBL+u8HT22UjxFnWl7hwnZBeckaqgAhTK9hVTz1xxI8U83219bJ3+EGbRHvZhwmTIBqGaoy+x1L0JTRnLsMccyAT4Yqo1vR1lN12gIMVpl57/diGbvO4yMJt4+RYskU6ow17FOPBSE4+4T9CHYAaS3mTXCFByUq3Ewcju8HYpdmH0d2o/pWciJio4aRcI/SPSBUExLUdwHdwxjjwNxs5n8ICaVgtfbNq1WfP0T3gLIUtvm8GVIctupU17mrhrVgi79gQcIGmY6lLxq3gXT0Wy2/IbzrQpiQDGPJMPHHFaEueqKHvwUZhl9//EUWNSfCGpkXeCmg1L/p+ocsrKZcq3XVBBMz/FXewp+CJDtCfFBIQN0+8iKTUaUSVIQxg05wrH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 06:58:38.4199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 918d2d1a-24e5-4acb-f1e0-08de78f24c15 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9451 From: Vidya Sagar Currently, the default setting is that CLKREQ# signal of a Root Port is internally overridden to '0' to enable REFCLK to flow out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the downstream side of the switch and expecting the Endpoint devices to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch drives the CLKREQ# of the Root Port itself low to avoid link up issues between PCIe switch downstream port and Endpoint devices. This is not a wrong thing to do after all the CLKREQ# is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V6 -> V7: Fix commit message Changes V1 -> V6: None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b1ae46761915..2f1f882fc737 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -44,6 +44,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1411,6 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } -- 2.34.1