[PATCH v7 0/9] Enhancements to pcie-tegra194 driver

[PATCH v7 0/9] Enhancements to pcie-tegra194 driver

[Manikanta Maddireddy]

This series[1] was originally posted by Vidya Sagar, and I have rebased
it onto 6.19.0-rc6-next. I addressed review comments and split this into
two series, one for fixes and the other is for enhancements(current).
I verified these patches on Jetson AGX Orin(Tegra234 SoC).

Disabling L1SS capability based on support-clkreq device tree property
is moved to common DWC driver, so I reworked below patch to disable
just L1.2 capability on Tegra234 SoC.
 - PCI: tegra194: Disable L1.2 capability of Tegra234 EP

I added below new patch to tune the ASPM parameters, commit message of the
patch has the details on the bug and fix.
 - PCI: tegra194: Add ASPM L1 entrance latency config

I added more context in the commit message for below patch based on review
comment in V3.
 - PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration

Rest of the patches are same as the original V3 series, just rebased them on
6.19.0-rc6-next and fixed minor comments.

Manikanta Maddireddy (1):
  PCI: tegra194: Add ASPM L1 entrance latency config

Vidya Sagar (8):
  PCI: tegra194: Drive CLKREQ# signal low explicitly
  PCI: tegra194: Calibrate P2U for Endpoint mode
  PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt
    registration
  PCI: tegra194: Enable DMA interrupt
  PCI: tegra194: Enable hardware hot reset mode in Endpoint
  PCI: tegra194: Disable L1.2 capability of Tegra234 EP
  dt-bindings: PCI: tegra194: Add monitor clock support
  PCI: tegra194: Add core monitor clock support

 .../bindings/pci/nvidia,tegra194-pcie-ep.yaml |  6 +-
 .../bindings/pci/nvidia,tegra194-pcie.yaml    |  6 +-
 drivers/pci/controller/dwc/pcie-tegra194.c    | 67 ++++++++++++++++++-
 3 files changed, 76 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Currently, the default setting is that CLKREQ# signal of a Root Port
is internally overridden to '0' to enable REFCLK to flow out to the slot.
It is observed that one of the PCIe switches (case in point Broadcom PCIe
Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
downstream side of the switch and expecting the Endpoint devices to pull
it low so that it (PCIe switch) can give out the REFCLK although the Switch
as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
patch drives the CLKREQ# of the Root Port itself low to avoid link up
issues between PCIe switch downstream port and Endpoint devices. This is
not a wrong thing to do after all the CLKREQ# is anyway being overridden
to '0' internally and now it is just that the same is being propagated
outside also.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: Fix commit message
Changes V1 -> V6: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b1ae46761915..2f1f882fc737 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -44,6 +44,7 @@
 #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
+#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE	BIT(13)
 
 #define APPL_CTRL				0x4
 #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
@@ -1411,6 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
 		val = appl_readl(pcie, APPL_PINMUX);
 		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
 		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
+		val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;
 		appl_writel(pcie, val, APPL_PINMUX);
 	}
 
-- 
2.34.1

Re: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:50PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Currently, the default setting is that CLKREQ# signal of a Root Port
> is internally overridden to '0' to enable REFCLK to flow out to the slot.
> It is observed that one of the PCIe switches (case in point Broadcom PCIe
> Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
> downstream side of the switch and expecting the Endpoint devices to pull
> it low so that it (PCIe switch) can give out the REFCLK although the Switch
> as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
> patch drives the CLKREQ# of the Root Port itself low to avoid link up
> issues between PCIe switch downstream port and Endpoint devices. This is

Is the CLKREQ# signal shared with the switch and the endpoint devices
connected to its downstream port also?

> not a wrong thing to do after all the CLKREQ# is anyway being overridden
> to '0' internally and now it is just that the same is being propagated
> outside also.
> 

What do you mean by 'propagating outside'?

And what is the difference between APPL_PINMUX_CLKREQ_OVERRIDE and
APPL_PINMUX_CLKREQ_DEFAULT_VALUE?

- Mani

> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V6 -> V7: Fix commit message
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index b1ae46761915..2f1f882fc737 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -44,6 +44,7 @@
>  #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
> +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE	BIT(13)
>  
>  #define APPL_CTRL				0x4
>  #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
> @@ -1411,6 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>  		val = appl_readl(pcie, APPL_PINMUX);
>  		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
>  		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
> +		val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;
>  		appl_writel(pcie, val, APPL_PINMUX);
>  	}
>  
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manikanta Maddireddy]

On 05/03/26 4:28 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:27:50PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Currently, the default setting is that CLKREQ# signal of a Root Port
>> is internally overridden to '0' to enable REFCLK to flow out to the slot.
>> It is observed that one of the PCIe switches (case in point Broadcom PCIe
>> Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
>> downstream side of the switch and expecting the Endpoint devices to pull
>> it low so that it (PCIe switch) can give out the REFCLK although the Switch
>> as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
>> patch drives the CLKREQ# of the Root Port itself low to avoid link up
>> issues between PCIe switch downstream port and Endpoint devices. This is
> 
> Is the CLKREQ# signal shared with the switch and the endpoint devices
> connected to its downstream port also?
> 
Yes, this is the observation.

>> not a wrong thing to do after all the CLKREQ# is anyway being overridden
>> to '0' internally and now it is just that the same is being propagated
>> outside also.
>>
> 
> What do you mean by 'propagating outside'?
> 
> And what is the difference between APPL_PINMUX_CLKREQ_OVERRIDE and
> APPL_PINMUX_CLKREQ_DEFAULT_VALUE?
> 
> - Mani
APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# input PAD to PCIe 
controller.
APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# output PAD to low.
Propagating outside means driving CLKREQ# pin as low.

- Manikanta

> 
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V6 -> V7: Fix commit message
>> Changes V1 -> V6: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index b1ae46761915..2f1f882fc737 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -44,6 +44,7 @@
>>   #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>>   #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>>   #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
>> +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE	BIT(13)
>>   
>>   #define APPL_CTRL				0x4
>>   #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
>> @@ -1411,6 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>>   		val = appl_readl(pcie, APPL_PINMUX);
>>   		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
>>   		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
>> +		val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;
>>   		appl_writel(pcie, val, APPL_PINMUX);
>>   	}
>>   
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 10:46:08PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 4:28 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:27:50PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Currently, the default setting is that CLKREQ# signal of a Root Port
> > > is internally overridden to '0' to enable REFCLK to flow out to the slot.
> > > It is observed that one of the PCIe switches (case in point Broadcom PCIe
> > > Gen4 switch) is propagating the CLKREQ# signal of the Root Port to the
> > > downstream side of the switch and expecting the Endpoint devices to pull
> > > it low so that it (PCIe switch) can give out the REFCLK although the Switch
> > > as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this
> > > patch drives the CLKREQ# of the Root Port itself low to avoid link up
> > > issues between PCIe switch downstream port and Endpoint devices. This is
> > 
> > Is the CLKREQ# signal shared with the switch and the endpoint devices
> > connected to its downstream port also?
> > 
> Yes, this is the observation.
> 
> > > not a wrong thing to do after all the CLKREQ# is anyway being overridden
> > > to '0' internally and now it is just that the same is being propagated
> > > outside also.
> > > 
> > 
> > What do you mean by 'propagating outside'?
> > 
> > And what is the difference between APPL_PINMUX_CLKREQ_OVERRIDE and
> > APPL_PINMUX_CLKREQ_DEFAULT_VALUE?
> > 
> > - Mani
> APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# input PAD to PCIe
> controller.
> APPL_PINMUX_CLKREQ_OVERRIDE: This overrides CLKREQ# output PAD to low.
> Propagating outside means driving CLKREQ# pin as low.
> 

From the commit message, it looks like APPL_PINMUX_CLKREQ_OVERRIDE itself
drivers the CLKREQ# signal to low (0), so it is not clear to me what this new
APPL_PINMUX_CLKREQ_DEFAULT_VALUE setting does.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 2/9] PCI: tegra194: Calibrate P2U for Endpoint mode

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Calibrate P2U for Endpoint controller to request UPHY PLL rate change to
Gen1 during initialization. This helps to reset stale PLL state from the
previous bad link state.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 2f1f882fc737..980988b7499c 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1054,6 +1054,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
 		ret = phy_power_on(pcie->phys[i]);
 		if (ret < 0)
 			goto phy_exit;
+
+		if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
+			phy_calibrate(pcie->phys[i]);
 	}
 
 	return 0;
-- 
2.34.1

Re: [PATCH v7 2/9] PCI: tegra194: Calibrate P2U for Endpoint mode

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:51PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Calibrate P2U for Endpoint controller to request UPHY PLL rate change to

What is P2U?

- Mani

> Gen1 during initialization. This helps to reset stale PLL state from the
> previous bad link state.
> 
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 2f1f882fc737..980988b7499c 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1054,6 +1054,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
>  		ret = phy_power_on(pcie->phys[i]);
>  		if (ret < 0)
>  			goto phy_exit;
> +
> +		if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
> +			phy_calibrate(pcie->phys[i]);
>  	}
>  
>  	return 0;
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 2/9] PCI: tegra194: Calibrate P2U for Endpoint mode

[Manikanta Maddireddy]

On 05/03/26 4:29 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:27:51PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Calibrate P2U for Endpoint controller to request UPHY PLL rate change to
> 
> What is P2U?
> 
> - Mani
It is pipe to "universal PHY(analog PHY)" wrapper which connects DWC 
core and UPHY.

- Manikanta
> 
>> Gen1 during initialization. This helps to reset stale PLL state from the
>> previous bad link state.
>>
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V1 -> V7: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 2f1f882fc737..980988b7499c 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1054,6 +1054,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
>>   		ret = phy_power_on(pcie->phys[i]);
>>   		if (ret < 0)
>>   			goto phy_exit;
>> +
>> +		if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
>> +			phy_calibrate(pcie->phys[i]);
>>   	}
>>   
>>   	return 0;
>> -- 
>> 2.34.1
>>
> 

-- 
nvpublic

Re: [PATCH v7 2/9] PCI: tegra194: Calibrate P2U for Endpoint mode

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 10:47:55PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 4:29 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:27:51PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Calibrate P2U for Endpoint controller to request UPHY PLL rate change to
> > 
> > What is P2U?
> > 
> > - Mani
> It is pipe to "universal PHY(analog PHY)" wrapper which connects DWC core
> and UPHY.
> 

Okay, please expand it in commit message.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

The Tegra PCIe Endpoint controller has a single interrupt line that is
shared between multiple interrupt sources:
1. PCIe link state events (link up, hot reset done)
2. Configuration space events (Bus Master Enable changes)
3. DMA completion events

Currently, the interrupt is registered with IRQF_ONESHOT, which keeps the
interrupt line masked until the threaded handler completes. This prevents
the DMA driver from sharing the same interrupt line, as the DMA completion
interrupts would be blocked while the threaded handler processes link state
events.

Removing IRQF_ONESHOT is safe for the following reasons:

1. The hard IRQ handler (tegra_pcie_ep_hard_irq) properly acknowledges and
   clears all interrupt status bits in hardware before returning. This
   prevents interrupt storms and ensures the interrupt controller can
   re-enable the interrupt line immediately.

2. The hard IRQ handler explicitly checks for DMA interrupts
   (APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) and marks them as handled,
   allowing the DMA driver's handler to process them separately.

3. The threaded handler (tegra_pcie_ep_irq_thread) only processes link-up
   notifications and LTR message sending. These operations don't conflict
   with DMA interrupt processing and don't require the interrupt line to
   remain masked.

This change enables the DMA driver to share the interrupt line with the
PCIe Endpoint driver, allowing both drivers to process their respective
events without blocking each other.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V6 -> V7: None
Changes V1 -> V6: Updated commit message

 drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 980988b7499c..352412680b4d 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2227,7 +2227,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 		ret = devm_request_threaded_irq(dev, pp->irq,
 						tegra_pcie_ep_hard_irq,
 						tegra_pcie_ep_irq_thread,
-						IRQF_SHARED | IRQF_ONESHOT,
+						IRQF_SHARED,
 						"tegra-pcie-ep-intr", pcie);
 		if (ret) {
 			dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
-- 
2.34.1

Re: [PATCH v7 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:52PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> The Tegra PCIe Endpoint controller has a single interrupt line that is
> shared between multiple interrupt sources:
> 1. PCIe link state events (link up, hot reset done)
> 2. Configuration space events (Bus Master Enable changes)
> 3. DMA completion events
> 
> Currently, the interrupt is registered with IRQF_ONESHOT, which keeps the
> interrupt line masked until the threaded handler completes. This prevents
> the DMA driver from sharing the same interrupt line, as the DMA completion
> interrupts would be blocked while the threaded handler processes link state
> events.
> 
> Removing IRQF_ONESHOT is safe for the following reasons:
> 
> 1. The hard IRQ handler (tegra_pcie_ep_hard_irq) properly acknowledges and
>    clears all interrupt status bits in hardware before returning. This
>    prevents interrupt storms and ensures the interrupt controller can
>    re-enable the interrupt line immediately.
> 
> 2. The hard IRQ handler explicitly checks for DMA interrupts
>    (APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) and marks them as handled,
>    allowing the DMA driver's handler to process them separately.
> 

Is this change actually present in the upstream driver? I can't see it, but just
the definition of APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK.

> 3. The threaded handler (tegra_pcie_ep_irq_thread) only processes link-up
>    notifications and LTR message sending. These operations don't conflict
>    with DMA interrupt processing and don't require the interrupt line to
>    remain masked.
> 
> This change enables the DMA driver to share the interrupt line with the
> PCIe Endpoint driver, allowing both drivers to process their respective
> events without blocking each other.
> 

I don't know how the DMA driver can share the interrupt requested by the
endpoint controller driver.

- Mani

> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V6 -> V7: None
> Changes V1 -> V6: Updated commit message
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 980988b7499c..352412680b4d 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2227,7 +2227,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>  		ret = devm_request_threaded_irq(dev, pp->irq,
>  						tegra_pcie_ep_hard_irq,
>  						tegra_pcie_ep_irq_thread,
> -						IRQF_SHARED | IRQF_ONESHOT,
> +						IRQF_SHARED,
>  						"tegra-pcie-ep-intr", pcie);
>  		if (ret) {
>  			dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration

[Manivannan Sadhasivam]

On Thu, Mar 05, 2026 at 04:33:04PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:27:52PM +0530, Manikanta Maddireddy wrote:
> > From: Vidya Sagar <vidyas@nvidia.com>
> > 
> > The Tegra PCIe Endpoint controller has a single interrupt line that is
> > shared between multiple interrupt sources:
> > 1. PCIe link state events (link up, hot reset done)
> > 2. Configuration space events (Bus Master Enable changes)
> > 3. DMA completion events
> > 
> > Currently, the interrupt is registered with IRQF_ONESHOT, which keeps the
> > interrupt line masked until the threaded handler completes. This prevents
> > the DMA driver from sharing the same interrupt line, as the DMA completion
> > interrupts would be blocked while the threaded handler processes link state
> > events.
> > 
> > Removing IRQF_ONESHOT is safe for the following reasons:
> > 
> > 1. The hard IRQ handler (tegra_pcie_ep_hard_irq) properly acknowledges and
> >    clears all interrupt status bits in hardware before returning. This
> >    prevents interrupt storms and ensures the interrupt controller can
> >    re-enable the interrupt line immediately.
> > 
> > 2. The hard IRQ handler explicitly checks for DMA interrupts
> >    (APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) and marks them as handled,
> >    allowing the DMA driver's handler to process them separately.
> > 
> 
> Is this change actually present in the upstream driver? I can't see it, but just
> the definition of APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK.
> 

Ok, I see this change in the next patch. But this wording is wrong as it implies
that the driver currently handles it.

> > 3. The threaded handler (tegra_pcie_ep_irq_thread) only processes link-up
> >    notifications and LTR message sending. These operations don't conflict
> >    with DMA interrupt processing and don't require the interrupt line to
> >    remain masked.
> > 
> > This change enables the DMA driver to share the interrupt line with the
> > PCIe Endpoint driver, allowing both drivers to process their respective
> > events without blocking each other.
> > 
> 
> I don't know how the DMA driver can share the interrupt requested by the
> endpoint controller driver.
> 

Same here.

- Mani

> - Mani
> 
> > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > Tested-by: Jon Hunter <jonathanh@nvidia.com>
> > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > ---
> > Changes V6 -> V7: None
> > Changes V1 -> V6: Updated commit message
> > 
> >  drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > index 980988b7499c..352412680b4d 100644
> > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > @@ -2227,7 +2227,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
> >  		ret = devm_request_threaded_irq(dev, pp->irq,
> >  						tegra_pcie_ep_hard_irq,
> >  						tegra_pcie_ep_irq_thread,
> > -						IRQF_SHARED | IRQF_ONESHOT,
> > +						IRQF_SHARED,
> >  						"tegra-pcie-ep-intr", pcie);
> >  		if (ret) {
> >  			dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
> > -- 
> > 2.34.1
> > 
> 
> -- 
> மணிவண்ணன் சதாசிவம்

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 4/9] PCI: tegra194: Enable DMA interrupt

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Enable DMA interrupt to support Tegra PCIe DMA in both Root Port and
Endpoint modes.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 352412680b4d..918e864b74a7 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -91,6 +91,7 @@
 #define APPL_INTR_EN_L1_8_0			0x44
 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN		BIT(2)
 #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN	BIT(3)
+#define APPL_INTR_EN_L1_8_EDMA_INT_EN		BIT(6)
 #define APPL_INTR_EN_L1_8_INTX_EN		BIT(11)
 #define APPL_INTR_EN_L1_8_AER_INT_EN		BIT(15)
 
@@ -543,6 +544,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
 		spurious = 0;
 	}
 
+	if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
+		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
+		/* Interrupt is handled by dma driver, don't treat it as spurious */
+		if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)
+			spurious = 0;
+	}
+
 	if (spurious) {
 		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
 			 status_l0);
@@ -762,6 +770,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)
 	val |= APPL_INTR_EN_L1_8_INTX_EN;
 	val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
 	val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
+	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
 	if (IS_ENABLED(CONFIG_PCIEAER))
 		val |= APPL_INTR_EN_L1_8_AER_INT_EN;
 	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
@@ -1786,6 +1795,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
 	val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
 	val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
+	val |= APPL_INTR_EN_L0_0_INT_INT_EN;
 	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
 
 	val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
@@ -1793,6 +1803,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
 	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
 
+	val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
+	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
+	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
+
 	/* 110us for both snoop and no-snoop */
 	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
 	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
-- 
2.34.1

Re: [PATCH v7 4/9] PCI: tegra194: Enable DMA interrupt

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:53PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Enable DMA interrupt to support Tegra PCIe DMA in both Root Port and
> Endpoint modes.
> 
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 352412680b4d..918e864b74a7 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -91,6 +91,7 @@
>  #define APPL_INTR_EN_L1_8_0			0x44
>  #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN		BIT(2)
>  #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN	BIT(3)
> +#define APPL_INTR_EN_L1_8_EDMA_INT_EN		BIT(6)
>  #define APPL_INTR_EN_L1_8_INTX_EN		BIT(11)
>  #define APPL_INTR_EN_L1_8_AER_INT_EN		BIT(15)
>  
> @@ -543,6 +544,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>  		spurious = 0;
>  	}
>  
> +	if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
> +		/* Interrupt is handled by dma driver, don't treat it as spurious */

Ok, so the eDMA driver also requests the IRQ as shared (threaded)...

- Mani

> +		if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)
> +			spurious = 0;
> +	}
> +
>  	if (spurious) {
>  		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
>  			 status_l0);
> @@ -762,6 +770,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)
>  	val |= APPL_INTR_EN_L1_8_INTX_EN;
>  	val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
>  	val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
> +	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
>  	if (IS_ENABLED(CONFIG_PCIEAER))
>  		val |= APPL_INTR_EN_L1_8_AER_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
> @@ -1786,6 +1795,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
>  	val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
>  	val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;
> +	val |= APPL_INTR_EN_L0_0_INT_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>  
>  	val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
> @@ -1793,6 +1803,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>  
> +	val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
> +	val |= APPL_INTR_EN_L1_8_EDMA_INT_EN;
> +	appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
> +
>  	/* 110us for both snoop and no-snoop */
>  	val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
>  	      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

When PCIe link goes down, hardware can retrain the link and try to link up.
To enable this feature, program the APPL_CTRL register with hardware hot
reset with immediate LTSSM enable mode.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 918e864b74a7..8f95910e99bc 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1772,6 +1772,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val = appl_readl(pcie, APPL_CTRL);
 	val |= APPL_CTRL_SYS_PRE_DET_STATE;
 	val |= APPL_CTRL_HW_HOT_RST_EN;
+	val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+	val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
 	appl_writel(pcie, val, APPL_CTRL);
 
 	val = appl_readl(pcie, APPL_CFG_MISC);
-- 
2.34.1

[PATCH v7 6/9] PCI: tegra194: Disable L1.2 capability of Tegra234 EP

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

When Tegra234 is operating in the Endpoint mode with L1.2 enabled, PCIe
link goes down during L1.2 exit. This is because Tegra234 is powering up
UPHY PLL immediately without making sure that the REFCLK is stable.
This is causing UPHY PLL to not lock to the correct frequency and leading
to link going down. There is no hardware fix for this, hence do not
advertise the L1.2 capability in the Endpoint mode.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 8f95910e99bc..070eb7f4058d 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -236,6 +236,7 @@ struct tegra_pcie_dw_of_data {
 	bool has_sbr_reset_fix;
 	bool has_l1ss_exit_fix;
 	bool has_ltr_req_fix;
+	bool disable_l1_2;
 	u32 cdm_chk_int_en_bit;
 	u32 gen4_preset_vec;
 	u8 n_fts[2];
@@ -688,6 +689,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	if (pcie->supports_clkreq)
 		pci->l1ss_support = true;
 
+	/*
+	 * Disable L1.2 capability advertisement for Tegra234 Endpoint mode.
+	 * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is
+	 * powered up immediately without waiting for REFCLK to stabilize. This
+	 * causes the PLL to fail to lock to the correct frequency, resulting in
+	 * PCIe link loss. Since there is no hardware fix available, we prevent
+	 * the Endpoint from advertising L1.2 support by clearing the L1.2 bits
+	 * in the L1 PM Substates Capabilities register. This ensures the host
+	 * will not attempt to enter L1.2 state with this Endpoint.
+	 */
+	if (pcie->of_data->disable_l1_2 && pcie->of_data->mode == DW_PCIE_EP_TYPE) {
+		val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
+		val &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2);
+		dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);
+	}
+
 	/* Program L0s and L1 entrance latencies */
 	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
 	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
@@ -2465,6 +2482,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
 	.mode = DW_PCIE_EP_TYPE,
 	.has_l1ss_exit_fix = true,
 	.has_ltr_req_fix = true,
+	.disable_l1_2 = true,
 	.cdm_chk_int_en_bit = BIT(18),
 	/* Gen4 - 6, 8 and 9 presets enabled */
 	.gen4_preset_vec = 0x340,
-- 
2.34.1

Re: [PATCH v7 6/9] PCI: tegra194: Disable L1.2 capability of Tegra234 EP

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:55PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> When Tegra234 is operating in the Endpoint mode with L1.2 enabled, PCIe
> link goes down during L1.2 exit. This is because Tegra234 is powering up
> UPHY PLL immediately without making sure that the REFCLK is stable.
> This is causing UPHY PLL to not lock to the correct frequency and leading
> to link going down. There is no hardware fix for this, hence do not
> advertise the L1.2 capability in the Endpoint mode.
> 
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>

There should be Fixes tag pointing to the commit that added Tegra234 support.

- Mani

> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 8f95910e99bc..070eb7f4058d 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -236,6 +236,7 @@ struct tegra_pcie_dw_of_data {
>  	bool has_sbr_reset_fix;
>  	bool has_l1ss_exit_fix;
>  	bool has_ltr_req_fix;
> +	bool disable_l1_2;
>  	u32 cdm_chk_int_en_bit;
>  	u32 gen4_preset_vec;
>  	u8 n_fts[2];
> @@ -688,6 +689,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>  	if (pcie->supports_clkreq)
>  		pci->l1ss_support = true;
>  
> +	/*
> +	 * Disable L1.2 capability advertisement for Tegra234 Endpoint mode.
> +	 * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is
> +	 * powered up immediately without waiting for REFCLK to stabilize. This
> +	 * causes the PLL to fail to lock to the correct frequency, resulting in
> +	 * PCIe link loss. Since there is no hardware fix available, we prevent
> +	 * the Endpoint from advertising L1.2 support by clearing the L1.2 bits
> +	 * in the L1 PM Substates Capabilities register. This ensures the host
> +	 * will not attempt to enter L1.2 state with this Endpoint.
> +	 */
> +	if (pcie->of_data->disable_l1_2 && pcie->of_data->mode == DW_PCIE_EP_TYPE) {
> +		val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
> +		val &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2);
> +		dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);
> +	}
> +
>  	/* Program L0s and L1 entrance latencies */
>  	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>  	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
> @@ -2465,6 +2482,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
>  	.mode = DW_PCIE_EP_TYPE,
>  	.has_l1ss_exit_fix = true,
>  	.has_ltr_req_fix = true,
> +	.disable_l1_2 = true,
>  	.cdm_chk_int_en_bit = BIT(18),
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 7/9] dt-bindings: PCI: tegra194: Add monitor clock support

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Tegra supports PCIe core clock monitoring for any rate changes that may be
happening because of the link speed changes. This is useful in tracking
any changes in the core clock that are not initiated by the software.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V5 -> V7: None
Changes V4 -> V5: Fixed clock description per review comment
Changes V1 -> V4: None

 .../devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml    | 6 +++++-
 .../devicetree/bindings/pci/nvidia,tegra194-pcie.yaml       | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
index 6d6052a2748f..7805757f2e2d 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
@@ -55,12 +55,16 @@ properties:
       - const: intr
 
   clocks:
+    minItems: 1
     items:
-      - description: module clock
+      - description: core clock
+      - description: monitor clock
 
   clock-names:
+    minItems: 1
     items:
       - const: core
+      - const: core_m
 
   resets:
     items:
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
index fe81d52c7277..41041ae7e0a4 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
@@ -58,12 +58,16 @@ properties:
       - const: msi
 
   clocks:
+    minItems: 1
     items:
-      - description: module clock
+      - description: core clock
+      - description: monitor clock
 
   clock-names:
+    minItems: 1
     items:
       - const: core
+      - const: core_m
 
   resets:
     items:
-- 
2.34.1

[PATCH v7 8/9] PCI: tegra194: Add core monitor clock support

[Manikanta Maddireddy]

From: Vidya Sagar <vidyas@nvidia.com>

Tegra supports PCIe core clock monitoring for any rate changes that may be
happening because of the link speed changes. This is useful in tracking
any changes in the core clock that are not initiated by the software. This
patch adds support to parse the monitor clock info from device-tree and
enable it if present.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 070eb7f4058d..e0455d322166 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -249,6 +249,7 @@ struct tegra_pcie_dw {
 	struct resource *atu_dma_res;
 	void __iomem *appl_base;
 	struct clk *core_clk;
+	struct clk *core_clk_m;
 	struct reset_control *core_apb_rst;
 	struct reset_control *core_rst;
 	struct dw_pcie pci;
@@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
 	}
 
 	clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
+	if (clk_prepare_enable(pcie->core_clk_m))
+		dev_err(pci->dev, "Failed to enable core monitor clock\n");
 
 	return 0;
 }
@@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
 		val &= ~PCI_DLF_EXCHANGE_ENABLE;
 		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
 
+		/*
+		 * core_clk_m is enabled as part of host_init callback in
+		 * dw_pcie_host_init(). Disable the clock since below
+		 * tegra_pcie_dw_host_init() will enable it again.
+		 */
+		clk_disable_unprepare(pcie->core_clk_m);
 		tegra_pcie_dw_host_init(pp);
 		dw_pcie_setup_rc(pp);
 
@@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 
 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
 {
+	clk_disable_unprepare(pcie->core_clk_m);
 	dw_pcie_host_deinit(&pcie->pci.pp);
 	tegra_pcie_dw_pme_turnoff(pcie);
 	tegra_pcie_unconfig_controller(pcie);
@@ -2161,6 +2171,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
 		return PTR_ERR(pcie->core_clk);
 	}
 
+	pcie->core_clk_m = devm_clk_get_optional(dev, "core_m");
+	if (IS_ERR(pcie->core_clk_m)) {
+		dev_err(dev, "Failed to get monitor clock: %ld\n",
+			PTR_ERR(pcie->core_clk_m));
+		return PTR_ERR(pcie->core_clk_m);
+	}
+
 	pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 						      "appl");
 	if (!pcie->appl_res) {
@@ -2357,6 +2374,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
 	if (!pcie->link_state)
 		return 0;
 
+	clk_disable_unprepare(pcie->core_clk_m);
 	tegra_pcie_dw_pme_turnoff(pcie);
 	tegra_pcie_unconfig_controller(pcie);
 
-- 
2.34.1

Re: [PATCH v7 8/9] PCI: tegra194: Add core monitor clock support

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:57PM +0530, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> Tegra supports PCIe core clock monitoring for any rate changes that may be
> happening because of the link speed changes. This is useful in tracking
> any changes in the core clock that are not initiated by the software. This
> patch adds support to parse the monitor clock info from device-tree and
> enable it if present.
> 

Reword the description in imperative mood and avoid 'This patch...'.

> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 070eb7f4058d..e0455d322166 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -249,6 +249,7 @@ struct tegra_pcie_dw {
>  	struct resource *atu_dma_res;
>  	void __iomem *appl_base;
>  	struct clk *core_clk;
> +	struct clk *core_clk_m;
>  	struct reset_control *core_apb_rst;
>  	struct reset_control *core_rst;
>  	struct dw_pcie pci;
> @@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
>  	}
>  
>  	clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
> +	if (clk_prepare_enable(pcie->core_clk_m))
> +		dev_err(pci->dev, "Failed to enable core monitor clock\n");
>  
>  	return 0;
>  }
> @@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
>  		val &= ~PCI_DLF_EXCHANGE_ENABLE;
>  		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
>  
> +		/*
> +		 * core_clk_m is enabled as part of host_init callback in
> +		 * dw_pcie_host_init(). Disable the clock since below
> +		 * tegra_pcie_dw_host_init() will enable it again.
> +		 */
> +		clk_disable_unprepare(pcie->core_clk_m);

Again, this change should be in a separate patch.

>  		tegra_pcie_dw_host_init(pp);
>  		dw_pcie_setup_rc(pp);
>  
> @@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>  
>  static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>  {
> +	clk_disable_unprepare(pcie->core_clk_m);
>  	dw_pcie_host_deinit(&pcie->pci.pp);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
> @@ -2161,6 +2171,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>  		return PTR_ERR(pcie->core_clk);
>  	}
>  
> +	pcie->core_clk_m = devm_clk_get_optional(dev, "core_m");
> +	if (IS_ERR(pcie->core_clk_m)) {
> +		dev_err(dev, "Failed to get monitor clock: %ld\n",
> +			PTR_ERR(pcie->core_clk_m));

To simplify, just do:

		return dev_err_probe();

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 8/9] PCI: tegra194: Add core monitor clock support

[Manikanta Maddireddy]

On 05/03/26 4:42 pm, Manivannan Sadhasivam wrote:
> On Tue, Mar 03, 2026 at 12:27:57PM +0530, Manikanta Maddireddy wrote:
>> From: Vidya Sagar <vidyas@nvidia.com>
>>
>> Tegra supports PCIe core clock monitoring for any rate changes that may be
>> happening because of the link speed changes. This is useful in tracking
>> any changes in the core clock that are not initiated by the software. This
>> patch adds support to parse the monitor clock info from device-tree and
>> enable it if present.
>>
> 
> Reword the description in imperative mood and avoid 'This patch...'.
> 
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> Changes V1 -> V7: None
>>
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
>>   1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 070eb7f4058d..e0455d322166 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -249,6 +249,7 @@ struct tegra_pcie_dw {
>>   	struct resource *atu_dma_res;
>>   	void __iomem *appl_base;
>>   	struct clk *core_clk;
>> +	struct clk *core_clk_m;
>>   	struct reset_control *core_apb_rst;
>>   	struct reset_control *core_rst;
>>   	struct dw_pcie pci;
>> @@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
>>   	}
>>   
>>   	clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>> +	if (clk_prepare_enable(pcie->core_clk_m))
>> +		dev_err(pci->dev, "Failed to enable core monitor clock\n");
>>   
>>   	return 0;
>>   }
>> @@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
>>   		val &= ~PCI_DLF_EXCHANGE_ENABLE;
>>   		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
>>   
>> +		/*
>> +		 * core_clk_m is enabled as part of host_init callback in
>> +		 * dw_pcie_host_init(). Disable the clock since below
>> +		 * tegra_pcie_dw_host_init() will enable it again.
>> +		 */
>> +		clk_disable_unprepare(pcie->core_clk_m);
> 
> Again, this change should be in a separate patch.
This patch is handling only one feature, which is enabling monitor 
clock. Monitor clock is enabled in tegra_pcie_dw_host_init(), this 
function is executed twice when handling DLFE fix, so this line is 
disabling the clock before executing tegra_pcie_dw_host_init() 2nd time.
I think one patch is sufficient for this, otherwise it will introduce 
unbalanced clock enable error.

- Manikanta
> 
>>   		tegra_pcie_dw_host_init(pp);
>>   		dw_pcie_setup_rc(pp);
>>   
>> @@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>>   
>>   static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>>   {
>> +	clk_disable_unprepare(pcie->core_clk_m);
>>   	dw_pcie_host_deinit(&pcie->pci.pp);
>>   	tegra_pcie_dw_pme_turnoff(pcie);
>>   	tegra_pcie_unconfig_controller(pcie);
>> @@ -2161,6 +2171,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
>>   		return PTR_ERR(pcie->core_clk);
>>   	}
>>   
>> +	pcie->core_clk_m = devm_clk_get_optional(dev, "core_m");
>> +	if (IS_ERR(pcie->core_clk_m)) {
>> +		dev_err(dev, "Failed to get monitor clock: %ld\n",
>> +			PTR_ERR(pcie->core_clk_m));
> 
> To simplify, just do:
> 
> 		return dev_err_probe();
> 
> - Mani
> 

-- 
nvpublic

Re: [PATCH v7 8/9] PCI: tegra194: Add core monitor clock support

[Manivannan Sadhasivam]

On Sun, Mar 15, 2026 at 11:36:30PM +0530, Manikanta Maddireddy wrote:
> 
> 
> On 05/03/26 4:42 pm, Manivannan Sadhasivam wrote:
> > On Tue, Mar 03, 2026 at 12:27:57PM +0530, Manikanta Maddireddy wrote:
> > > From: Vidya Sagar <vidyas@nvidia.com>
> > > 
> > > Tegra supports PCIe core clock monitoring for any rate changes that may be
> > > happening because of the link speed changes. This is useful in tracking
> > > any changes in the core clock that are not initiated by the software. This
> > > patch adds support to parse the monitor clock info from device-tree and
> > > enable it if present.
> > > 
> > 
> > Reword the description in imperative mood and avoid 'This patch...'.
> > 
> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > > Tested-by: Jon Hunter <jonathanh@nvidia.com>
> > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > ---
> > > Changes V1 -> V7: None
> > > 
> > >   drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++
> > >   1 file changed, 18 insertions(+)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > index 070eb7f4058d..e0455d322166 100644
> > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > @@ -249,6 +249,7 @@ struct tegra_pcie_dw {
> > >   	struct resource *atu_dma_res;
> > >   	void __iomem *appl_base;
> > >   	struct clk *core_clk;
> > > +	struct clk *core_clk_m;
> > >   	struct reset_control *core_apb_rst;
> > >   	struct reset_control *core_rst;
> > >   	struct dw_pcie pci;
> > > @@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> > >   	}
> > >   	clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
> > > +	if (clk_prepare_enable(pcie->core_clk_m))
> > > +		dev_err(pci->dev, "Failed to enable core monitor clock\n");
> > >   	return 0;
> > >   }
> > > @@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
> > >   		val &= ~PCI_DLF_EXCHANGE_ENABLE;
> > >   		dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
> > > +		/*
> > > +		 * core_clk_m is enabled as part of host_init callback in
> > > +		 * dw_pcie_host_init(). Disable the clock since below
> > > +		 * tegra_pcie_dw_host_init() will enable it again.
> > > +		 */
> > > +		clk_disable_unprepare(pcie->core_clk_m);
> > 
> > Again, this change should be in a separate patch.
> This patch is handling only one feature, which is enabling monitor clock.
> Monitor clock is enabled in tegra_pcie_dw_host_init(), this function is
> executed twice when handling DLFE fix, so this line is disabling the clock
> before executing tegra_pcie_dw_host_init() 2nd time.
> I think one patch is sufficient for this, otherwise it will introduce
> unbalanced clock enable error.
> 

Oh yes, brain fart. You can ignore the above comment.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v7 9/9] PCI: tegra194: Add ASPM L1 entrance latency config

[Manikanta Maddireddy]

For Tegra234, the HW PHY team conducted experiments and determined the
optimal ASPM L1 entrance latency values: 8 us for Root Port mode and
16 us for Endpoint mode. Update the default ASPM L1 entrance latency
configuration accordingly.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None

 drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index e0455d322166..accb2f8d3de8 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -240,6 +240,8 @@ struct tegra_pcie_dw_of_data {
 	u32 cdm_chk_int_en_bit;
 	u32 gen4_preset_vec;
 	u8 n_fts[2];
+	/* L1 Latency entrance values(Rest/Prod) */
+	u32 aspm_l1_enter_lat;
 };
 
 struct tegra_pcie_dw {
@@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
 	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
 	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
+	val |= (pcie->of_data->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
 	val |= PORT_AFR_ENTER_ASPM;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
 }
@@ -2472,6 +2476,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {
 	/* Gen4 - 5, 6, 8 and 9 presets enabled */
 	.gen4_preset_vec = 0x360,
 	.n_fts = { 52, 52 },
+	.aspm_l1_enter_lat = 3,
 };
 
 static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
@@ -2481,6 +2486,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
 	/* Gen4 - 5, 6, 8 and 9 presets enabled */
 	.gen4_preset_vec = 0x360,
 	.n_fts = { 52, 52 },
+	.aspm_l1_enter_lat = 3,
 };
 
 static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
@@ -2493,6 +2499,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
 	/* Gen4 - 6, 8 and 9 presets enabled */
 	.gen4_preset_vec = 0x340,
 	.n_fts = { 52, 80 },
+	.aspm_l1_enter_lat = 4,
 };
 
 static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
@@ -2505,6 +2512,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
 	/* Gen4 - 6, 8 and 9 presets enabled */
 	.gen4_preset_vec = 0x340,
 	.n_fts = { 52, 80 },
+	.aspm_l1_enter_lat = 5,
 };
 
 static const struct of_device_id tegra_pcie_dw_of_match[] = {
-- 
2.34.1

Re: [PATCH v7 9/9] PCI: tegra194: Add ASPM L1 entrance latency config

[Manivannan Sadhasivam]

On Tue, Mar 03, 2026 at 12:27:58PM +0530, Manikanta Maddireddy wrote:
> For Tegra234, the HW PHY team conducted experiments and determined the
> optimal ASPM L1 entrance latency values: 8 us for Root Port mode and
> 16 us for Endpoint mode. Update the default ASPM L1 entrance latency
> configuration accordingly.
> 

Can you please make use of the new 'aspm-l1-entry-delay-ns' devicetree property?

- Mani

> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> Tested-by: Jon Hunter <jonathanh@nvidia.com>
> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V7: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index e0455d322166..accb2f8d3de8 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -240,6 +240,8 @@ struct tegra_pcie_dw_of_data {
>  	u32 cdm_chk_int_en_bit;
>  	u32 gen4_preset_vec;
>  	u8 n_fts[2];
> +	/* L1 Latency entrance values(Rest/Prod) */
> +	u32 aspm_l1_enter_lat;
>  };
>  
>  struct tegra_pcie_dw {
> @@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
>  	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
>  	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
>  	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
> +	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
> +	val |= (pcie->of_data->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
>  	val |= PORT_AFR_ENTER_ASPM;
>  	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
>  }
> @@ -2472,6 +2476,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {
>  	/* Gen4 - 5, 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x360,
>  	.n_fts = { 52, 52 },
> +	.aspm_l1_enter_lat = 3,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
> @@ -2481,6 +2486,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
>  	/* Gen4 - 5, 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x360,
>  	.n_fts = { 52, 52 },
> +	.aspm_l1_enter_lat = 3,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
> @@ -2493,6 +2499,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,
>  	.n_fts = { 52, 80 },
> +	.aspm_l1_enter_lat = 4,
>  };
>  
>  static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
> @@ -2505,6 +2512,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
>  	/* Gen4 - 6, 8 and 9 presets enabled */
>  	.gen4_preset_vec = 0x340,
>  	.n_fts = { 52, 80 },
> +	.aspm_l1_enter_lat = 5,
>  };
>  
>  static const struct of_device_id tegra_pcie_dw_of_match[] = {
> -- 
> 2.34.1
> 

-- 
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