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Mon, 2 Mar 2026 22:58:32 -0800 From: Manikanta Maddireddy To: , , , , , , , , , , , , , , , , , , <18255117159@163.com> CC: , , , Manikanta Maddireddy Subject: [PATCH v7 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Date: Tue, 3 Mar 2026 12:27:52 +0530 Message-ID: <20260303065758.2364340-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260303065758.2364340-1-mmaddireddy@nvidia.com> References: <20260303065758.2364340-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBC:EE_|MN2PR12MB4126:EE_ X-MS-Office365-Filtering-Correlation-Id: b211d869-5d18-443c-f840-08de78f2588d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013|921020; X-Microsoft-Antispam-Message-Info: eQsGKL21+53ncz2QE7IdBxUMwsAH/Yy3Z3Gg2I6EJUjWxndeHw/VBleCJeJHgVRpdLj63oAEJ0jIs/PniYm8UTGfmnAlGZTQ0cLhdB0d8QYJp3SWU9olzE46fss1gWCxf/Q3GWasrnfwPcdbO6zBqIJzlcDpI8OzM0Ik+pSJ7RNgqbN38KYSUlBLRwF0yO4kxp0ztcuhqW3SJZp0sCOk0bURq+S7KAsOjWShLvtl82jvRJPTBusTE/g3u06NYv1bdHvaZf/YFODgeLatMEElTgUHVDF+u2yyO7HfnCHW6JO7XYbFbnR4Fn7lFQ0tJRWFo8Ob/SmSvyVnGQW8YU/2/V6H1l77TfZojW6O27Q1laMwI2OlnZ0v76ZcZ8U5LJ6vCEKCqovhRU6vE2pBQi0XrawotmbG7ZzdkHwJrP50qhDu8pfv8WtCImRKNrmr0dMAm/cZU37800LuVPZEksKoRW8CCnRaDPA2KNdhZOdQfFf616kJUD7O+lYmilA5vzb+IMGeuz8VmykcQk8qWrje2dwSAvTM1IIsJjRsfPt13EmM9Fw5eOd2mPnyU62/gW3TNKpcM/Yv9bo9Y0EOU4jsNZkQ+k3GUFhtyfhtoPhU72hKAqRgb1J6gfvjqXZ5haiYegrYUKqBRDt6pwgEdOoEBTQBReVs2M9hDoMwqFSueweKfstR38bkLnBOnrrtYZq/YMDQAcl0vUSsd5oNikgdnCWoV4QIC4zfgKZTBtHGw10KRzjoT3jcgp1h+9ikaKpGiDmBaoVL9atajzeCYIdN90fMKlMa1JIA0KZsIttuYSf1oz/JPx/R2d2ivENZO0CumX/a2hIm5BJNQNxrrdm7kIp1f6CQYy7uCfBMAPP9GS0= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ch6pTlSuzg/fvUFToRmSD/JO+ZbROe7HHmC6eH4/E0jF4jr07KxYH/TdTnQH6+e0mkl3N4EC47cr1oTWC7e27NIDH7pGbmMCRJVzRhwG29DUE99gNI58uezDZ3m3Ik07JfIWSmqNsnh2eEVUmCaNEA47qy5/LRHn6zrqc7nFkTd7er+9dfEbtmJq0+gN0PmEtxy29TK73Zek1x6oJ72XYYql2xEvGSAi0490kfa6WI7Tu6+8gWRBHmxHGGedhMOmb8YgCyEi8iT5VYYOGUl1iJC4qGL+shpoBgHhaQ8xgu8zgHKz4UfWVkMn7v56aUjW7r5SNA7u3dDTTQW3X2Oi1kb5fRQ7tubY4N79/17vcxewhWH20j/kIuKtOQwpO9SqAAYmXRz5/D4zL+JvvNXs1VWjRLPHTrxMPi1Fco5dRZyDUsGdChwyQ5MGxpjsjZYF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2026 06:58:59.4033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b211d869-5d18-443c-f840-08de78f2588d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4126 From: Vidya Sagar The Tegra PCIe Endpoint controller has a single interrupt line that is shared between multiple interrupt sources: 1. PCIe link state events (link up, hot reset done) 2. Configuration space events (Bus Master Enable changes) 3. DMA completion events Currently, the interrupt is registered with IRQF_ONESHOT, which keeps the interrupt line masked until the threaded handler completes. This prevents the DMA driver from sharing the same interrupt line, as the DMA completion interrupts would be blocked while the threaded handler processes link state events. Removing IRQF_ONESHOT is safe for the following reasons: 1. The hard IRQ handler (tegra_pcie_ep_hard_irq) properly acknowledges and clears all interrupt status bits in hardware before returning. This prevents interrupt storms and ensures the interrupt controller can re-enable the interrupt line immediately. 2. The hard IRQ handler explicitly checks for DMA interrupts (APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) and marks them as handled, allowing the DMA driver's handler to process them separately. 3. The threaded handler (tegra_pcie_ep_irq_thread) only processes link-up notifications and LTR message sending. These operations don't conflict with DMA interrupt processing and don't require the interrupt line to remain masked. This change enables the DMA driver to share the interrupt line with the PCIe Endpoint driver, allowing both drivers to process their respective events without blocking each other. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V6 -> V7: None Changes V1 -> V6: Updated commit message drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 980988b7499c..352412680b4d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2227,7 +2227,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) ret = devm_request_threaded_irq(dev, pp->irq, tegra_pcie_ep_hard_irq, tegra_pcie_ep_irq_thread, - IRQF_SHARED | IRQF_ONESHOT, + IRQF_SHARED, "tegra-pcie-ep-intr", pcie); if (ret) { dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, -- 2.34.1