From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <mani@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
<kishon@kernel.org>, <arnd@arndb.de>,
<gregkh@linuxfoundation.org>, <Frank.Li@nxp.com>,
<den@valinux.co.jp>, <hongxing.zhu@nxp.com>,
<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,
<18255117159@163.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH v7 5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint
Date: Tue, 3 Mar 2026 12:27:54 +0530 [thread overview]
Message-ID: <20260303065758.2364340-6-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20260303065758.2364340-1-mmaddireddy@nvidia.com>
From: Vidya Sagar <vidyas@nvidia.com>
When PCIe link goes down, hardware can retrain the link and try to link up.
To enable this feature, program the APPL_CTRL register with hardware hot
reset with immediate LTSSM enable mode.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
Changes V1 -> V7: None
drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 918e864b74a7..8f95910e99bc 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1772,6 +1772,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val = appl_readl(pcie, APPL_CTRL);
val |= APPL_CTRL_SYS_PRE_DET_STATE;
val |= APPL_CTRL_HW_HOT_RST_EN;
+ val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
appl_writel(pcie, val, APPL_CTRL);
val = appl_readl(pcie, APPL_CFG_MISC);
--
2.34.1
next prev parent reply other threads:[~2026-03-03 6:59 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-03 6:57 [PATCH v7 0/9] Enhancements to pcie-tegra194 driver Manikanta Maddireddy
2026-03-03 6:57 ` [PATCH v7 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly Manikanta Maddireddy
2026-03-05 10:58 ` Manivannan Sadhasivam
2026-03-15 17:16 ` Manikanta Maddireddy
2026-03-16 3:26 ` Manivannan Sadhasivam
2026-03-03 6:57 ` [PATCH v7 2/9] PCI: tegra194: Calibrate P2U for Endpoint mode Manikanta Maddireddy
2026-03-05 10:59 ` Manivannan Sadhasivam
2026-03-15 17:17 ` Manikanta Maddireddy
2026-03-16 3:27 ` Manivannan Sadhasivam
2026-03-03 6:57 ` [PATCH v7 3/9] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Manikanta Maddireddy
2026-03-05 11:02 ` Manivannan Sadhasivam
2026-03-05 11:04 ` Manivannan Sadhasivam
2026-03-03 6:57 ` [PATCH v7 4/9] PCI: tegra194: Enable DMA interrupt Manikanta Maddireddy
2026-03-05 11:06 ` Manivannan Sadhasivam
2026-03-03 6:57 ` Manikanta Maddireddy [this message]
2026-03-03 6:57 ` [PATCH v7 6/9] PCI: tegra194: Disable L1.2 capability of Tegra234 EP Manikanta Maddireddy
2026-03-05 11:09 ` Manivannan Sadhasivam
2026-03-03 6:57 ` [PATCH v7 7/9] dt-bindings: PCI: tegra194: Add monitor clock support Manikanta Maddireddy
2026-03-03 6:57 ` [PATCH v7 8/9] PCI: tegra194: Add core " Manikanta Maddireddy
2026-03-05 11:12 ` Manivannan Sadhasivam
2026-03-15 18:06 ` Manikanta Maddireddy
2026-03-16 3:30 ` Manivannan Sadhasivam
2026-03-03 6:57 ` [PATCH v7 9/9] PCI: tegra194: Add ASPM L1 entrance latency config Manikanta Maddireddy
2026-03-05 11:15 ` Manivannan Sadhasivam
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