* [PATCH v2 01/10] dt-bindings: phy: tegra-xusb: Document Type C support
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
@ 2026-02-23 14:32 ` Thierry Reding
2026-03-06 0:02 ` Rob Herring (Arm)
2026-02-23 14:32 ` [PATCH 02/10] dt-bindings: pci: tegra: Convert to json-schema Thierry Reding
` (9 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Each XUSB PHY can be hooked up to a Type C controller via a port
property, so document this in the bindings accordingly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- make one of port or connector a dependency of usb-role-switch
.../phy/nvidia,tegra194-xusb-padctl.yaml | 39 ++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
index 6e3398399628..d8de900a4fce 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
@@ -230,6 +230,10 @@ properties:
connector:
type: object
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
mode:
description: A string that determines the mode in which to
run the port.
@@ -256,7 +260,12 @@ properties:
voltage.
dependencies:
- usb-role-switch: [ connector ]
+ usb-role-switch:
+ oneOf:
+ - required:
+ - connector
+ - required:
+ - port
usb2-1:
type: object
@@ -268,6 +277,10 @@ properties:
connector:
type: object
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
mode:
description: A string that determines the mode in which to
run the port.
@@ -306,6 +319,10 @@ properties:
connector:
type: object
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
mode:
description: A string that determines the mode in which to
run the port.
@@ -344,6 +361,10 @@ properties:
connector:
type: object
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
mode:
description: A string that determines the mode in which to
run the port.
@@ -405,6 +426,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
usb3-1:
type: object
additionalProperties: false
@@ -438,6 +463,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
usb3-2:
type: object
additionalProperties: false
@@ -471,6 +500,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
usb3-3:
type: object
additionalProperties: false
@@ -504,6 +537,10 @@ properties:
description: A phandle to the regulator supplying the VBUS
voltage.
+ port:
+ description: connection to a USB Type C controller
+ $ref: /schemas/graph.yaml#/properties/port
+
additionalProperties: false
required:
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 01/10] dt-bindings: phy: tegra-xusb: Document Type C support
2026-02-23 14:32 ` [PATCH v2 01/10] dt-bindings: phy: tegra-xusb: Document Type C support Thierry Reding
@ 2026-03-06 0:02 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2026-03-06 0:02 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, Conor Dooley, Krzysztof Kozlowski, devicetree,
linux-tegra
On Mon, 23 Feb 2026 15:32:56 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Each XUSB PHY can be hooked up to a Type C controller via a port
> property, so document this in the bindings accordingly.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - make one of port or connector a dependency of usb-role-switch
>
> .../phy/nvidia,tegra194-xusb-padctl.yaml | 39 ++++++++++++++++++-
> 1 file changed, 38 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 02/10] dt-bindings: pci: tegra: Convert to json-schema
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
2026-02-23 14:32 ` [PATCH v2 01/10] dt-bindings: phy: tegra-xusb: Document Type C support Thierry Reding
@ 2026-02-23 14:32 ` Thierry Reding
2026-03-06 0:19 ` Rob Herring
2026-02-23 14:32 ` [PATCH v3 03/10] dt-bindings: clock: tegra124-dfll: " Thierry Reding
` (8 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra PCIe controller bindings from the free-form text
format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v5:
- drop unneeded quotes
Changes in v4:
- remove path references
- use dual licensing
Changes in v3:
- fixup reference in MAINTAINERS
Changes in v2:
- drop description properties where they don't add information
- drop redundant $ref properties
.../bindings/pci/nvidia,tegra20-pcie.txt | 670 --------------
.../bindings/pci/nvidia,tegra20-pcie.yaml | 851 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 852 insertions(+), 671 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
deleted file mode 100644
index d099f3476ccc..000000000000
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ /dev/null
@@ -1,670 +0,0 @@
-NVIDIA Tegra PCIe controller
-
-Required properties:
-- compatible: Must be:
- - "nvidia,tegra20-pcie": for Tegra20
- - "nvidia,tegra30-pcie": for Tegra30
- - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
- - "nvidia,tegra210-pcie": for Tegra210
- - "nvidia,tegra186-pcie": for Tegra186
-- power-domains: To ungate power partition by BPMP powergate driver. Must
- contain BPMP phandle and PCIe power partition ID. This is required only
- for Tegra186.
-- device_type: Must be "pci"
-- reg: A list of physical base address and length for each set of controller
- registers. Must contain an entry for each entry in the reg-names property.
-- reg-names: Must include the following entries:
- "pads": PADS registers
- "afi": AFI registers
- "cs": configuration space region
-- interrupts: A list of interrupt outputs of the controller. Must contain an
- entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The Tegra interrupt that is asserted for controller interrupts
- "msi": The Tegra interrupt that is asserted when an MSI is received
-- bus-range: Range of bus numbers associated with this controller
-- #address-cells: Address representation for root ports (must be 3)
- - cell 0 specifies the bus and device numbers of the root port:
- [23:16]: bus number
- [15:11]: device number
- - cell 1 denotes the upper 32 address bits and should be 0
- - cell 2 contains the lower 32 address bits and is used to translate to the
- CPU address space
-- #size-cells: Size representation for root ports (must be 2)
-- ranges: Describes the translation of addresses for root ports and standard
- PCI regions. The entries must be 6 cells each, where the first three cells
- correspond to the address as described for the #address-cells property
- above, the fourth cell is the physical CPU address to translate to and the
- fifth and six cells are as described for the #size-cells property above.
- - The first two entries are expected to translate the addresses for the root
- port registers, which are referenced by the assigned-addresses property of
- the root port nodes (see below).
- - The remaining entries setup the mapping for the standard I/O, memory and
- prefetchable PCI regions. The first cell determines the type of region
- that is setup:
- - 0x81000000: I/O memory region
- - 0x82000000: non-prefetchable memory region
- - 0xc2000000: prefetchable memory region
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - pex
- - afi
- - pll_e
- - cml (not required for Tegra20)
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - pex
- - afi
- - pcie_x
-
-Optional properties:
-- pinctrl-names: A list of pinctrl state names. Must contain the following
- entries:
- - "default": active state, puts PCIe I/O out of deep power down state
- - "idle": puts PCIe I/O into deep power down state
-- pinctrl-0: phandle for the default/active state of pin configurations.
-- pinctrl-1: phandle for the idle state of pin configurations.
-
-Required properties on Tegra124 and later (deprecated):
-- phys: Must contain an entry for each entry in phy-names.
-- phy-names: Must include the following entries:
- - pcie
-
-These properties are deprecated in favour of per-lane PHYs define in each of
-the root ports (see below).
-
-Power supplies for Tegra20:
-- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
-- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
-- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
- supply 1.05 V.
-- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
- supply 1.05 V.
-- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
-
-Power supplies for Tegra30:
-- Required:
- - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
- supply 1.05 V.
- - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
- supply 1.05 V.
- - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
- supply 1.8 V.
- - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
- Must supply 3.3 V.
-- Optional:
- - If lanes 0 to 3 are used:
- - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- - If lanes 4 or 5 are used:
- - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
-
-Power supplies for Tegra124:
-- Required:
- - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
- - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
- Must supply 3.3 V.
- - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
- supply 2.8-3.3 V.
-
-Power supplies for Tegra210:
-- Required:
- - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
- clocks. Must supply 1.8 V.
- - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
- supply 1.8 V.
-
-Power supplies for Tegra186:
-- Required:
- - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
- - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
- supply 1.8 V.
- - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
- Must supply 1.8 V.
- - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
- supply 1.8 V.
-
-Root ports are defined as subnodes of the PCIe controller node.
-
-Required properties:
-- device_type: Must be "pci"
-- assigned-addresses: Address and size of the port configuration registers
-- reg: PCI bus address of the root port
-- #address-cells: Must be 3
-- #size-cells: Must be 2
-- ranges: Sub-ranges distributed from the PCIe controller node. An empty
- property is sufficient.
-- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
- are:
- - Root port 0 uses 4 lanes, root port 1 is unused.
- - Both root ports use 2 lanes.
-
-Required properties for Tegra124 and later:
-- phys: Must contain an phandle to a PHY for each entry in phy-names.
-- phy-names: Must include an entry for each active lane. Note that the number
- of entries does not have to (though usually will) be equal to the specified
- number of lanes in the nvidia,num-lanes property. Entries are of the form
- "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
-
-Examples:
-=========
-
-Tegra20:
---------
-
-SoC DTSI:
-
- pcie-controller@80003000 {
- compatible = "nvidia,tegra20-pcie";
- device_type = "pci";
- reg = <0x80003000 0x00000800 /* PADS registers */
- 0x80003800 0x00000200 /* AFI registers */
- 0x90000000 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
- interrupts = <0 98 0x04 /* controller interrupt */
- 0 99 0x04>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
- 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
- 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
- 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
-
- clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
- clock-names = "pex", "afi", "pll_e";
- resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
- reset-names = "pex", "afi", "pcie_x";
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges;
-
- nvidia,num-lanes = <2>;
- };
- };
-
-Board DTS:
-
- pcie-controller@80003000 {
- status = "okay";
-
- vdd-supply = <&pci_vdd_reg>;
- pex-clk-supply = <&pci_clk_reg>;
-
- /* root port 00:01.0 */
- pci@1,0 {
- status = "okay";
-
- /* bridge 01:00.0 (optional) */
- pci@0,0 {
- reg = <0x010000 0 0 0 0>;
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- device_type = "pci";
-
- /* endpoint 02:00.0 */
- pci@0,0 {
- reg = <0x020000 0 0 0 0>;
- };
- };
- };
- };
-
-Note that devices on the PCI bus are dynamically discovered using PCI's bus
-enumeration and therefore don't need corresponding device nodes in DT. However
-if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
-device nodes need to be added in order to allow the bus' children to be
-instantiated at the proper location in the operating system's device tree (as
-illustrated by the optional nodes in the example above).
-
-Tegra30:
---------
-
-SoC DTSI:
-
- pcie-controller@3000 {
- compatible = "nvidia,tegra30-pcie";
- device_type = "pci";
- reg = <0x00003000 0x00000800 /* PADS registers */
- 0x00003800 0x00000200 /* AFI registers */
- 0x10000000 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
- GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
- 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
- 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
- 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
-
- clocks = <&tegra_car TEGRA30_CLK_PCIE>,
- <&tegra_car TEGRA30_CLK_AFI>,
- <&tegra_car TEGRA30_CLK_PLL_E>,
- <&tegra_car TEGRA30_CLK_CML0>;
- clock-names = "pex", "afi", "pll_e", "cml";
- resets = <&tegra_car 70>,
- <&tegra_car 72>,
- <&tegra_car 74>;
- reset-names = "pex", "afi", "pcie_x";
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
- reg = <0x001800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
- };
-
-Board DTS:
-
- pcie-controller@3000 {
- status = "okay";
-
- avdd-pexa-supply = <&ldo1_reg>;
- vdd-pexa-supply = <&ldo1_reg>;
- avdd-pexb-supply = <&ldo1_reg>;
- vdd-pexb-supply = <&ldo1_reg>;
- avdd-pex-pll-supply = <&ldo1_reg>;
- avdd-plle-supply = <&ldo1_reg>;
- vddio-pex-ctl-supply = <&sys_3v3_reg>;
- hvdd-pex-supply = <&sys_3v3_pexs_reg>;
-
- pci@1,0 {
- status = "okay";
- };
-
- pci@3,0 {
- status = "okay";
- };
- };
-
-Tegra124:
----------
-
-SoC DTSI:
-
- pcie-controller@1003000 {
- compatible = "nvidia,tegra124-pcie";
- device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
-
- clocks = <&tegra_car TEGRA124_CLK_PCIE>,
- <&tegra_car TEGRA124_CLK_AFI>,
- <&tegra_car TEGRA124_CLK_PLL_E>,
- <&tegra_car TEGRA124_CLK_CML0>;
- clock-names = "pex", "afi", "pll_e", "cml";
- resets = <&tegra_car 70>,
- <&tegra_car 72>,
- <&tegra_car 74>;
- reset-names = "pex", "afi", "pcie_x";
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <1>;
- };
- };
-
-Board DTS:
-
- pcie-controller@1003000 {
- status = "okay";
-
- avddio-pex-supply = <&vdd_1v05_run>;
- dvddio-pex-supply = <&vdd_1v05_run>;
- avdd-pex-pll-supply = <&vdd_1v05_run>;
- hvdd-pex-supply = <&vdd_3v3_lp0>;
- hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
- vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
- avdd-pll-erefe-supply = <&avdd_1v05_run>;
-
- /* Mini PCIe */
- pci@1,0 {
- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
- phy-names = "pcie-0";
- status = "okay";
- };
-
- /* Gigabit Ethernet */
- pci@2,0 {
- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
- phy-names = "pcie-0";
- status = "okay";
- };
- };
-
-Tegra210:
----------
-
-SoC DTSI:
-
- pcie-controller@1003000 {
- compatible = "nvidia,tegra210-pcie";
- device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
-
- clocks = <&tegra_car TEGRA210_CLK_PCIE>,
- <&tegra_car TEGRA210_CLK_AFI>,
- <&tegra_car TEGRA210_CLK_PLL_E>,
- <&tegra_car TEGRA210_CLK_CML0>;
- clock-names = "pex", "afi", "pll_e", "cml";
- resets = <&tegra_car 70>,
- <&tegra_car 72>,
- <&tegra_car 74>;
- reset-names = "pex", "afi", "pcie_x";
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <4>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <1>;
- };
- };
-
-Board DTS:
-
- pcie-controller@1003000 {
- status = "okay";
-
- avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
- hvddio-pex-supply = <&vdd_1v8>;
- dvddio-pex-supply = <&vdd_pex_1v05>;
- dvdd-pex-pll-supply = <&vdd_pex_1v05>;
- hvdd-pex-pll-e-supply = <&vdd_1v8>;
- vddio-pex-ctl-supply = <&vdd_1v8>;
-
- pci@1,0 {
- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
- <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
- <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
- <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
- phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
- status = "okay";
- };
-
- pci@2,0 {
- phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
- phy-names = "pcie-0";
- status = "okay";
- };
- };
-
-Tegra186:
----------
-
-SoC DTSI:
-
- pcie@10003000 {
- compatible = "nvidia,tegra186-pcie";
- power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
- device_type = "pci";
- reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
- reg-names = "pads", "afi", "cs";
-
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-
- bus-range = <0x00 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
- 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
- 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
- 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
-
- clocks = <&bpmp TEGRA186_CLK_AFI>,
- <&bpmp TEGRA186_CLK_PCIE>,
- <&bpmp TEGRA186_CLK_PLLE>;
- clock-names = "afi", "pex", "pll_e";
-
- resets = <&bpmp TEGRA186_RESET_AFI>,
- <&bpmp TEGRA186_RESET_PCIE>,
- <&bpmp TEGRA186_RESET_PCIEXCLK>;
- reset-names = "afi", "pex", "pcie_x";
-
- status = "disabled";
-
- pci@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
- reg = <0x000800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <2>;
- };
-
- pci@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
- reg = <0x001000 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <1>;
- };
-
- pci@3,0 {
- device_type = "pci";
- assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
- reg = <0x001800 0 0 0 0>;
- status = "disabled";
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- nvidia,num-lanes = <1>;
- };
- };
-
-Board DTS:
-
- pcie@10003000 {
- status = "okay";
-
- dvdd-pex-supply = <&vdd_pex>;
- hvdd-pex-pll-supply = <&vdd_1v8>;
- hvdd-pex-supply = <&vdd_1v8>;
- vddio-pexctl-aud-supply = <&vdd_1v8>;
-
- pci@1,0 {
- nvidia,num-lanes = <4>;
- status = "okay";
- };
-
- pci@2,0 {
- nvidia,num-lanes = <0>;
- status = "disabled";
- };
-
- pci@3,0 {
- nvidia,num-lanes = <1>;
- status = "disabled";
- };
- };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
new file mode 100644
index 000000000000..cfa8c27f6e9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
@@ -0,0 +1,851 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra20-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra PCIe controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra20-pcie
+ - nvidia,tegra30-pcie
+ - nvidia,tegra124-pcie
+ - nvidia,tegra210-pcie
+ - nvidia,tegra186-pcie
+
+ - items:
+ - const: nvidia,tegra132-pcie
+ - const: nvidia,tegra124-pcie
+
+ reg:
+ items:
+ - description: PADS registers
+ - description: AFI registers
+ - description: configuration space region
+
+ reg-names:
+ items:
+ - const: pads
+ - const: afi
+ - const: cs
+
+ interrupts:
+ items:
+ - description: PCIe controller interrupt
+ - description: MSI controller interrupt
+
+ interrupt-names:
+ items:
+ - const: intr
+ - const: msi
+
+ "#address-cells":
+ description: |
+ Address representation for root ports. Cell 0 specifies the bus and
+ device numbers of the root port:
+
+ [23:16]: bus number
+ [15:11]: device number
+
+ Cell 1 denotes the upper 32 address bits and should be 0, while cell 2
+ contains the lower 32 address bits and is used to translate to the CPU
+ address space.
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ clocks:
+ items:
+ - description: AFI interface clock
+ - description: PCI controller clock
+ - description: reference PLL clock
+ - description: CML clock
+ minItems: 3
+
+ clock-names:
+ items:
+ - const: pex
+ - const: afi
+ - const: pll_e
+ - const: cml
+ minItems: 3
+
+ resets:
+ items:
+ - description: AFI interface reset
+ - description: PCI controller reset
+ - description: PCI bus reset
+
+ reset-names:
+ items:
+ - const: pex
+ - const: afi
+ - const: pcie_x
+
+ interconnects:
+ items:
+ - description: AFI memory read client
+ - description: AFI memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ iommus:
+ maxItems: 1
+
+ operating-points-v2:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ power-domains:
+ items:
+ - description: phandle to the core power domain
+
+ pinctrl-names:
+ items:
+ # active state, puts PCIe I/O out of deep power down state
+ - const: default
+ # puts PCIe I/O into deep power down state
+ - const: idle
+
+patternProperties:
+ "^pci@1?[0-9a-f](,[0-7])?$":
+ description: Root ports are defined as subnodes of the PCIe controller
+ node.
+
+ Note that devices on the PCI bus are dynamically discovered using PCI's
+ bus enumeration and therefore don't need corresponding device nodes in
+ DT. However if a device on the PCI bus provides a non-probeable bus such
+ as I2C or SPI, device nodes need to be added in order to allow the bus'
+ children to be instantiated at the proper location in the operating
+ system's device tree (as illustrated by the optional nodes in the
+ examples below).
+
+ type: object
+ properties:
+ device_type:
+ const: pci
+
+ assigned-addresses:
+ description: Address and size of the port configuration registers
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ ranges:
+ description: Sub-ranges distributed from the PCIe controller node. An
+ empty property is sufficient.
+
+ nvidia,num-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of lanes to use for this port. Valid combinations
+ are:
+
+ - Root port 0 uses 4 lanes, root port 1 is unused.
+ - Both root ports use 2 lanes.
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: /schemas/pinctrl/pinctrl-consumer.yaml
+ - $ref: /schemas/pci/pci-bus.yaml
+ - $ref: pci-iommu.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra20-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ maxItems: 3
+
+ avdd-pex-supply:
+ description: Power supply for analog PCIe logic. Must supply 1.05 V.
+
+ vdd-pex-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+
+ avdd-pex-pll-supply:
+ description: Power supply for dedicated (internal) PCIe PLL. Must
+ supply 1.05 V.
+
+ avdd-plle-supply:
+ description: Power supply for PLLE, which is shared with SATA. Must
+ supply 1.05 V.
+
+ vddio-pex-clk-supply:
+ description: Power supply for PCIe clock. Must supply 3.3 V.
+
+ required:
+ - avdd-pex-supply
+ - vdd-pex-supply
+ - avdd-pex-pll-supply
+ - avdd-plle-supply
+ - vddio-pex-clk-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra30-pcie
+ then:
+ properties:
+ avdd-pex-pll-supply:
+ description: Power supply for dedicated (internal) PCIe PLL. Must
+ supply 1.05 V.
+
+ avdd-plle-supply:
+ description: Power supply for PLLE, which is shared with SATA. Must
+ supply 1.05 V.
+
+ vddio-pex-ctl-supply:
+ description: Power supply for PCIe control I/O partition. Must
+ supply 1.8 V.
+
+ hvdd-pex-supply:
+ description: High-voltage supply for PCIe I/O and PCIe output
+ clocks. Must supply 3.3 V.
+
+ avdd-pexa-supply:
+ description: Power supply for analog PCIe logic. Must supply 1.05 V.
+ Required if lanes 0 through 3 are used.
+
+ vdd-pexa-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+ Required if lanes 0 through 3 are used.
+
+ avdd-pexb-supply:
+ description: Power supply for analog PCIe logic. Must supply 1.05 V.
+ Required if lanes 4 and 5 are used.
+
+ vdd-pexb-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+ Required if lanes 4 and 5 are used.
+
+ required:
+ - avdd-pex-pll-supply
+ - avdd-plle-supply
+ - vddio-pex-ctl-supply
+ - hvdd-pex-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra124-pcie
+ then:
+ properties:
+ phys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ deprecated: true
+
+ phy-names:
+ items:
+ - const: pcie
+ deprecated: true
+
+ avddio-pex-supply:
+ description: Power supply for analog PCIe logic. Must supply 1.05 V.
+
+ dvddio-pex-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+
+ hvdd-pex-supply:
+ description: High-voltage supply for PCIe I/O and PCIe output
+ clocks. Must supply 3.3 V.
+
+ vddio-pex-ctl-supply:
+ description: Power supply for PCIe control I/O partition. Must
+ supply 2.8-3.3 V.
+
+ avdd-pex-pll-supply:
+ deprecated: true
+
+ hvdd-pex-pll-e-supply:
+ deprecated: true
+
+ avdd-pll-erefe-supply:
+ deprecated: true
+
+ required:
+ - avddio-pex-supply
+ - dvddio-pex-supply
+ - hvdd-pex-supply
+ - vddio-pex-ctl-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra210-pcie
+ then:
+ properties:
+ hvddio-pex-supply:
+ description: High-voltage supply for PCIe I/O and PCIe output
+ clocks. Must supply 1.8 V.
+
+ dvddio-pex-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+
+ vddio-pex-ctl-supply:
+ description: Power supply for PCIe control I/O partition. Must
+ supply 1.8 V.
+
+ avdd-pll-uerefe-supply:
+ deprecated: true
+
+ dvdd-pex-pll-supply:
+ deprecated: true
+
+ hvdd-pex-pll-e-supply:
+ deprecated: true
+
+ required:
+ - hvddio-pex-supply
+ - dvddio-pex-supply
+ - vddio-pex-ctl-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra186-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ maxItems: 3
+
+ power-domains:
+ description: To ungate power partition by BPMP powergate driver.
+ Must contain BPMP phandle and PCIe power partition ID.
+
+ dvdd-pex-supply:
+ description: Power supply for digital PCIe I/O. Must supply 1.05 V.
+
+ hvdd-pex-pll-supply:
+ description: High-voltage supply for PLLE (shared with USB3). Must
+ supply 1.8 V.
+
+ hvdd-pex-supply:
+ description: High-voltage supply for PCIe I/O and PCIe output
+ clocks. Must supply 1.8 V.
+
+ vddio-pexctl-aud-supply:
+ description: Power supply for PCIe side band signals. Must supply
+ 1.8 V.
+
+ required:
+ - dvdd-pex-supply
+ - hvdd-pex-pll-supply
+ - hvdd-pex-supply
+ - vddio-pexctl-aud-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra124-pcie
+ - nvidia,tegra210-pcie
+ - nvidia,tegra186-pcie
+ then:
+ patternProperties:
+ "^pci@1?[0-9a-f](,[0-7])?$":
+ properties:
+ phys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Must contain an phandle to a PHY for each entry in
+ phy-names.
+
+ phy-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Must include an entry for each active lane. Note
+ that the number of entries does not have to (though usually
+ will) be equal to the specified number of lanes in the
+ nvidia,num-lanes property. Entries are of the form "pcie-N",
+ where N ranges from 0 to the value specified in
+ nvidia,num-lanes.
+
+examples:
+ # Tegra20
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@80003000 {
+ compatible = "nvidia,tegra20-pcie";
+ device_type = "pci";
+ reg = <0x80003000 0x00000800>, /* PADS registers */
+ <0x80003800 0x00000200>, /* AFI registers */
+ <0x90000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <0 98 0x04>, /* controller interrupt */
+ <0 99 0x04>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
+ <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
+ <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
+ <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>, /* non-prefetchable memory */
+ <0x42000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
+
+ clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
+ clock-names = "pex", "afi", "pll_e";
+ resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
+ status = "okay";
+
+ avdd-pex-supply = <&pci_vdd_reg>;
+ vdd-pex-supply = <&pci_vdd_reg>;
+ avdd-pex-pll-supply = <&pci_vdd_reg>;
+ avdd-plle-supply = <&pci_vdd_reg>;
+ vddio-pex-clk-supply = <&pci_clk_reg>;
+
+ /* root port 00:01.0 */
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges;
+
+ nvidia,num-lanes = <2>;
+
+ /* bridge 01:00.0 (optional) */
+ pci@0,0 {
+ reg = <0x010000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ device_type = "pci";
+
+ /* endpoint 02:00.0 */
+ ethernet@0,0 {
+ reg = <0x020000 0 0 0 0>;
+ };
+ };
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+ };
+
+ # Tegra30
+ - |
+ #include <dt-bindings/clock/tegra30-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@3000 {
+ compatible = "nvidia,tegra30-pcie";
+ device_type = "pci";
+ reg = <0x00003000 0x00000800>, /* PADS registers */
+ <0x00003800 0x00000200>, /* AFI registers */
+ <0x10000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
+ <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
+ <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
+ <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
+ <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
+
+ clocks = <&tegra_car TEGRA30_CLK_PCIE>,
+ <&tegra_car TEGRA30_CLK_AFI>,
+ <&tegra_car TEGRA30_CLK_PLL_E>,
+ <&tegra_car TEGRA30_CLK_CML0>;
+ clock-names = "pex", "afi", "pll_e", "cml";
+ resets = <&tegra_car 70>,
+ <&tegra_car 72>,
+ <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
+ status = "okay";
+
+ avdd-pexa-supply = <&ldo1_reg>;
+ vdd-pexa-supply = <&ldo1_reg>;
+ avdd-pexb-supply = <&ldo1_reg>;
+ vdd-pexb-supply = <&ldo1_reg>;
+ avdd-pex-pll-supply = <&ldo1_reg>;
+ avdd-plle-supply = <&ldo1_reg>;
+ vddio-pex-ctl-supply = <&sys_3v3_reg>;
+ hvdd-pex-supply = <&sys_3v3_pexs_reg>;
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
+ reg = <0x001800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+ };
+
+ # Tegra124
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@1003000 {
+ compatible = "nvidia,tegra124-pcie";
+ device_type = "pci";
+ reg = <0x01003000 0x00000800>, /* PADS registers */
+ <0x01003800 0x00000800>, /* AFI registers */
+ <0x02000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x02000000 0 0x01000000 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+ clocks = <&tegra_car TEGRA124_CLK_PCIE>,
+ <&tegra_car TEGRA124_CLK_AFI>,
+ <&tegra_car TEGRA124_CLK_PLL_E>,
+ <&tegra_car TEGRA124_CLK_CML0>;
+ clock-names = "pex", "afi", "pll_e", "cml";
+ resets = <&tegra_car 70>,
+ <&tegra_car 72>,
+ <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
+ status = "okay";
+
+ avddio-pex-supply = <&vdd_1v05_run>;
+ dvddio-pex-supply = <&vdd_1v05_run>;
+ avdd-pex-pll-supply = <&vdd_1v05_run>;
+ hvdd-pex-supply = <&vdd_3v3_lp0>;
+ hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+ vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
+ avdd-pll-erefe-supply = <&avdd_1v05_run>;
+
+ /* Mini PCIe */
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+
+ phys = <&phy_pcie4>;
+ phy-names = "pcie-0";
+ };
+
+ /* Gigabit Ethernet */
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+
+ phys = <&phy_pcie2>;
+ phy-names = "pcie-0";
+ };
+ };
+
+ # Tegra210
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie@1003000 {
+ compatible = "nvidia,tegra210-pcie";
+ device_type = "pci";
+ reg = <0x01003000 0x00000800>, /* PADS registers */
+ <0x01003800 0x00000800>, /* AFI registers */
+ <0x02000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x02000000 0 0x01000000 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+ clocks = <&tegra_car TEGRA210_CLK_PCIE>,
+ <&tegra_car TEGRA210_CLK_AFI>,
+ <&tegra_car TEGRA210_CLK_PLL_E>,
+ <&tegra_car TEGRA210_CLK_CML0>;
+ clock-names = "pex", "afi", "pll_e", "cml";
+ resets = <&tegra_car 70>,
+ <&tegra_car 72>,
+ <&tegra_car 74>;
+ reset-names = "pex", "afi", "pcie_x";
+ status = "okay";
+
+ avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
+ hvddio-pex-supply = <&vdd_1v8>;
+ dvddio-pex-supply = <&vdd_pex_1v05>;
+ dvdd-pex-pll-supply = <&vdd_pex_1v05>;
+ hvdd-pex-pll-e-supply = <&vdd_1v8>;
+ vddio-pex-ctl-supply = <&vdd_1v8>;
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <4>;
+
+ phys = <&phy_pcie0>, <&phy_pcie1>, <&phy_pcie2>, <&phy_pcie3>;
+ phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+
+ phys = <&phy_pcie4>;
+ phy-names = "pcie-0";
+ };
+ };
+
+ # Tegra186
+ - |
+ #include <dt-bindings/clock/tegra186-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/power/tegra186-powergate.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ pcie@10003000 {
+ compatible = "nvidia,tegra186-pcie";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
+ device_type = "pci";
+ reg = <0x10003000 0x00000800>, /* PADS registers */
+ <0x10003800 0x00000800>, /* AFI registers */
+ <0x40000000 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x02000000 0 0x10000000 0x10000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x10001000 0x10001000 0 0x00001000>, /* port 1 configuration space */
+ <0x02000000 0 0x10004000 0x10004000 0 0x00001000>, /* port 2 configuration space */
+ <0x01000000 0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x50100000 0x50100000 0 0x07F00000>, /* non-prefetchable memory (127 MiB) */
+ <0x42000000 0 0x58000000 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+
+ clocks = <&bpmp TEGRA186_CLK_PCIE>,
+ <&bpmp TEGRA186_CLK_AFI>,
+ <&bpmp TEGRA186_CLK_PLLE>;
+ clock-names = "pex", "afi", "pll_e";
+
+ resets = <&bpmp TEGRA186_RESET_PCIE>,
+ <&bpmp TEGRA186_RESET_AFI>,
+ <&bpmp TEGRA186_RESET_PCIEXCLK>;
+ reset-names = "pex", "afi", "pcie_x";
+
+ iommus = <&smmu TEGRA186_SID_AFI>;
+ iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
+ iommu-map-mask = <0x0>;
+
+ status = "okay";
+
+ dvdd-pex-supply = <&vdd_pex>;
+ hvdd-pex-pll-supply = <&vdd_1v8>;
+ hvdd-pex-supply = <&vdd_1v8>;
+ vddio-pexctl-aud-supply = <&vdd_1v8>;
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "okay";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <4>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <0>;
+ };
+
+ pci@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
+ reg = <0x001800 0 0 0 0>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 71f76fddebbf..b010c4223e93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20255,7 +20255,7 @@ M: Thierry Reding <thierry.reding@kernel.org>
L: linux-tegra@vger.kernel.org
L: linux-pci@vger.kernel.org
S: Supported
-F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
F: drivers/pci/controller/pci-tegra.c
PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 02/10] dt-bindings: pci: tegra: Convert to json-schema
2026-02-23 14:32 ` [PATCH 02/10] dt-bindings: pci: tegra: Convert to json-schema Thierry Reding
@ 2026-03-06 0:19 ` Rob Herring
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2026-03-06 0:19 UTC (permalink / raw)
To: Thierry Reding
Cc: Krzysztof Kozlowski, Conor Dooley, Jon Hunter, devicetree,
linux-tegra
On Mon, Feb 23, 2026 at 03:32:57PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra PCIe controller bindings from the free-form text
> format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v5:
> - drop unneeded quotes
>
> Changes in v4:
> - remove path references
> - use dual licensing
>
> Changes in v3:
> - fixup reference in MAINTAINERS
>
> Changes in v2:
> - drop description properties where they don't add information
> - drop redundant $ref properties
>
> .../bindings/pci/nvidia,tegra20-pcie.txt | 670 --------------
> .../bindings/pci/nvidia,tegra20-pcie.yaml | 851 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 852 insertions(+), 671 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
> new file mode 100644
> index 000000000000..cfa8c27f6e9d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.yaml
> @@ -0,0 +1,851 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra20-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra PCIe controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - nvidia,tegra20-pcie
> + - nvidia,tegra30-pcie
> + - nvidia,tegra124-pcie
> + - nvidia,tegra210-pcie
> + - nvidia,tegra186-pcie
> +
> + - items:
> + - const: nvidia,tegra132-pcie
> + - const: nvidia,tegra124-pcie
> +
> + reg:
> + items:
> + - description: PADS registers
> + - description: AFI registers
> + - description: configuration space region
> +
> + reg-names:
> + items:
> + - const: pads
> + - const: afi
> + - const: cs
> +
> + interrupts:
> + items:
> + - description: PCIe controller interrupt
> + - description: MSI controller interrupt
> +
> + interrupt-names:
> + items:
> + - const: intr
> + - const: msi
> +
> + "#address-cells":
> + description: |
> + Address representation for root ports. Cell 0 specifies the bus and
> + device numbers of the root port:
> +
> + [23:16]: bus number
> + [15:11]: device number
> +
> + Cell 1 denotes the upper 32 address bits and should be 0, while cell 2
> + contains the lower 32 address bits and is used to translate to the CPU
> + address space.
> + const: 3
> +
> + "#size-cells":
> + const: 2
pci-host-bridge.yaml has both of these properties. Drop.
> +
> + clocks:
> + items:
> + - description: AFI interface clock
> + - description: PCI controller clock
> + - description: reference PLL clock
> + - description: CML clock
> + minItems: 3
> +
> + clock-names:
> + items:
> + - const: pex
> + - const: afi
> + - const: pll_e
> + - const: cml
> + minItems: 3
> +
> + resets:
> + items:
> + - description: AFI interface reset
> + - description: PCI controller reset
> + - description: PCI bus reset
> +
> + reset-names:
> + items:
> + - const: pex
> + - const: afi
> + - const: pcie_x
> +
> + interconnects:
> + items:
> + - description: AFI memory read client
> + - description: AFI memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + iommus:
> + maxItems: 1
> +
> + operating-points-v2:
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + power-domains:
> + items:
> + - description: phandle to the core power domain
> +
> + pinctrl-names:
> + items:
> + # active state, puts PCIe I/O out of deep power down state
> + - const: default
> + # puts PCIe I/O into deep power down state
> + - const: idle
> +
> +patternProperties:
> + "^pci@1?[0-9a-f](,[0-7])?$":
> + description: Root ports are defined as subnodes of the PCIe controller
> + node.
> +
> + Note that devices on the PCI bus are dynamically discovered using PCI's
> + bus enumeration and therefore don't need corresponding device nodes in
> + DT. However if a device on the PCI bus provides a non-probeable bus such
> + as I2C or SPI, device nodes need to be added in order to allow the bus'
> + children to be instantiated at the proper location in the operating
> + system's device tree (as illustrated by the optional nodes in the
> + examples below).
> +
> + type: object
$ref: /schemas/pci-pci-bridge.yaml#
unevaluatedProperties: false
> + properties:
> + device_type:
> + const: pci
> +
> + assigned-addresses:
> + description: Address and size of the port configuration registers
I think this should be 'reg' as the config registers aren't assignable.
> +
> + "#address-cells":
> + const: 3
> +
> + "#size-cells":
> + const: 2
> +
> + ranges:
> + description: Sub-ranges distributed from the PCIe controller node. An
> + empty property is sufficient.
Drop all the above.
> +
> + nvidia,num-lanes:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Number of lanes to use for this port. Valid combinations
> + are:
> +
> + - Root port 0 uses 4 lanes, root port 1 is unused.
> + - Both root ports use 2 lanes.
enum: [ 1, 2, 4 ]
> +
> +required:
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> +
> +unevaluatedProperties: false
> +
> +allOf:
> + - $ref: /schemas/pinctrl/pinctrl-consumer.yaml
> + - $ref: /schemas/pci/pci-bus.yaml
Deprecated. Use pci-host-bridge.yaml instead.
> + - $ref: pci-iommu.yaml
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra20-pcie
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + maxItems: 3
> +
> + avdd-pex-supply:
> + description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> + vdd-pex-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> + avdd-pex-pll-supply:
> + description: Power supply for dedicated (internal) PCIe PLL. Must
> + supply 1.05 V.
> +
> + avdd-plle-supply:
> + description: Power supply for PLLE, which is shared with SATA. Must
> + supply 1.05 V.
> +
> + vddio-pex-clk-supply:
> + description: Power supply for PCIe clock. Must supply 3.3 V.
> +
> + required:
> + - avdd-pex-supply
> + - vdd-pex-supply
> + - avdd-pex-pll-supply
> + - avdd-plle-supply
> + - vddio-pex-clk-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra30-pcie
> + then:
> + properties:
> + avdd-pex-pll-supply:
> + description: Power supply for dedicated (internal) PCIe PLL. Must
> + supply 1.05 V.
> +
> + avdd-plle-supply:
> + description: Power supply for PLLE, which is shared with SATA. Must
> + supply 1.05 V.
> +
> + vddio-pex-ctl-supply:
> + description: Power supply for PCIe control I/O partition. Must
> + supply 1.8 V.
> +
> + hvdd-pex-supply:
> + description: High-voltage supply for PCIe I/O and PCIe output
> + clocks. Must supply 3.3 V.
> +
> + avdd-pexa-supply:
> + description: Power supply for analog PCIe logic. Must supply 1.05 V.
> + Required if lanes 0 through 3 are used.
> +
> + vdd-pexa-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> + Required if lanes 0 through 3 are used.
> +
> + avdd-pexb-supply:
> + description: Power supply for analog PCIe logic. Must supply 1.05 V.
> + Required if lanes 4 and 5 are used.
> +
> + vdd-pexb-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> + Required if lanes 4 and 5 are used.
> +
> + required:
> + - avdd-pex-pll-supply
> + - avdd-plle-supply
> + - vddio-pex-ctl-supply
> + - hvdd-pex-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra124-pcie
> + then:
> + properties:
> + phys:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
phys already has a type. How many entries?
> + deprecated: true
> +
> + phy-names:
> + items:
> + - const: pcie
> + deprecated: true
> +
> + avddio-pex-supply:
> + description: Power supply for analog PCIe logic. Must supply 1.05 V.
> +
> + dvddio-pex-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> + hvdd-pex-supply:
> + description: High-voltage supply for PCIe I/O and PCIe output
> + clocks. Must supply 3.3 V.
> +
> + vddio-pex-ctl-supply:
> + description: Power supply for PCIe control I/O partition. Must
> + supply 2.8-3.3 V.
> +
> + avdd-pex-pll-supply:
> + deprecated: true
> +
> + hvdd-pex-pll-e-supply:
> + deprecated: true
> +
> + avdd-pll-erefe-supply:
> + deprecated: true
> +
> + required:
> + - avddio-pex-supply
> + - dvddio-pex-supply
> + - hvdd-pex-supply
> + - vddio-pex-ctl-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra210-pcie
> + then:
> + properties:
> + hvddio-pex-supply:
> + description: High-voltage supply for PCIe I/O and PCIe output
> + clocks. Must supply 1.8 V.
> +
> + dvddio-pex-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> + vddio-pex-ctl-supply:
> + description: Power supply for PCIe control I/O partition. Must
> + supply 1.8 V.
> +
> + avdd-pll-uerefe-supply:
> + deprecated: true
> +
> + dvdd-pex-pll-supply:
> + deprecated: true
> +
> + hvdd-pex-pll-e-supply:
> + deprecated: true
> +
> + required:
> + - hvddio-pex-supply
> + - dvddio-pex-supply
> + - vddio-pex-ctl-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra186-pcie
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + maxItems: 3
> +
> + power-domains:
> + description: To ungate power partition by BPMP powergate driver.
> + Must contain BPMP phandle and PCIe power partition ID.
> +
> + dvdd-pex-supply:
> + description: Power supply for digital PCIe I/O. Must supply 1.05 V.
> +
> + hvdd-pex-pll-supply:
> + description: High-voltage supply for PLLE (shared with USB3). Must
> + supply 1.8 V.
> +
> + hvdd-pex-supply:
> + description: High-voltage supply for PCIe I/O and PCIe output
> + clocks. Must supply 1.8 V.
> +
> + vddio-pexctl-aud-supply:
> + description: Power supply for PCIe side band signals. Must supply
> + 1.8 V.
> +
> + required:
> + - dvdd-pex-supply
> + - hvdd-pex-pll-supply
> + - hvdd-pex-supply
> + - vddio-pexctl-aud-supply
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra124-pcie
> + - nvidia,tegra210-pcie
> + - nvidia,tegra186-pcie
> + then:
> + patternProperties:
> + "^pci@1?[0-9a-f](,[0-7])?$":
$ref: /schemas/pci/pci-pci-bridge.yaml
unevaluatedProperties: false
But really, this should all be moved to the main schema above, and then
just use if/then schema to disallow these properties where they don't
apply.
> + properties:
> + phys:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type.
How many entries?
> + description: Must contain an phandle to a PHY for each entry in
> + phy-names.
> +
> + phy-names:
> + $ref: /schemas/types.yaml#/definitions/string-array
Already has a type.
> + description: Must include an entry for each active lane. Note
> + that the number of entries does not have to (though usually
> + will) be equal to the specified number of lanes in the
> + nvidia,num-lanes property. Entries are of the form "pcie-N",
> + where N ranges from 0 to the value specified in
> + nvidia,num-lanes.
Sounds like constraints.
> +
> +examples:
> + # Tegra20
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + pcie@80003000 {
> + compatible = "nvidia,tegra20-pcie";
> + device_type = "pci";
> + reg = <0x80003000 0x00000800>, /* PADS registers */
> + <0x80003800 0x00000200>, /* AFI registers */
> + <0x90000000 0x10000000>; /* configuration space */
> + reg-names = "pads", "afi", "cs";
> + interrupts = <0 98 0x04>, /* controller interrupt */
> + <0 99 0x04>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +
> + bus-range = <0x00 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
> + <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
> + <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
> + <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>, /* non-prefetchable memory */
> + <0x42000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
> +
> + clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
> + clock-names = "pex", "afi", "pll_e";
> + resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
> + reset-names = "pex", "afi", "pcie_x";
> + status = "okay";
> +
> + avdd-pex-supply = <&pci_vdd_reg>;
> + vdd-pex-supply = <&pci_vdd_reg>;
> + avdd-pex-pll-supply = <&pci_vdd_reg>;
> + avdd-plle-supply = <&pci_vdd_reg>;
> + vddio-pex-clk-supply = <&pci_clk_reg>;
> +
> + /* root port 00:01.0 */
> + pci@1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
> + reg = <0x000800 0 0 0 0>;
> + bus-range = <0x00 0xff>;
> + status = "okay";
Drop 'status'
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges;
> +
> + nvidia,num-lanes = <2>;
> +
> + /* bridge 01:00.0 (optional) */
> + pci@0,0 {
> + reg = <0x010000 0 0 0 0>;
> + bus-range = <0x00 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> +
> + device_type = "pci";
> +
> + /* endpoint 02:00.0 */
> + ethernet@0,0 {
> + reg = <0x020000 0 0 0 0>;
> + };
> + };
> + };
> +
> + pci@2,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
> + reg = <0x001000 0 0 0 0>;
> + bus-range = <0x00 0xff>;
> + status = "disabled";
Examples should be enabled. Drop.
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges;
> +
> + nvidia,num-lanes = <2>;
> + };
> + };
> +
> + # Tegra30
> + - |
Can we have just 1 or 2 examples that are substantually different. We
don't really need copies of what we have in real .dts files.
Rob
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 03/10] dt-bindings: clock: tegra124-dfll: Convert to json-schema
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
2026-02-23 14:32 ` [PATCH v2 01/10] dt-bindings: phy: tegra-xusb: Document Type C support Thierry Reding
2026-02-23 14:32 ` [PATCH 02/10] dt-bindings: pci: tegra: Convert to json-schema Thierry Reding
@ 2026-02-23 14:32 ` Thierry Reding
2026-03-06 0:22 ` Rob Herring (Arm)
2026-02-23 14:32 ` [PATCH 04/10] dt-bindings: interrupt-controller: tegra: Fix reg entries Thierry Reding
` (7 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra124 (and later) DFLL bindings from the free-form text
format to json-schema.
Co-developed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- adopt some changes from Rob's patch
- turn dependencies into if:then:else to correctly represent when
the vdd-cpu-supply property is needed
Changes in v2:
- license under GPL-2.0-only OR BSD-2-Clause
- add constraints for vendor properties
.../bindings/clock/nvidia,tegra124-dfll.txt | 155 ----------
.../bindings/clock/nvidia,tegra124-dfll.yaml | 290 ++++++++++++++++++
2 files changed, 290 insertions(+), 155 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
deleted file mode 100644
index f7d347385b57..000000000000
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
+++ /dev/null
@@ -1,155 +0,0 @@
-NVIDIA Tegra124 DFLL FCPU clocksource
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The DFLL IP block on Tegra is a root clocksource designed for clocking
-the fast CPU cluster. It consists of a free-running voltage controlled
-oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
-control module that will automatically adjust the VDD_CPU voltage by
-communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
-
-Required properties:
-- compatible : should be one of:
- - "nvidia,tegra124-dfll": for Tegra124
- - "nvidia,tegra210-dfll": for Tegra210
-- reg : Defines the following set of registers, in the order listed:
- - registers for the DFLL control logic.
- - registers for the I2C output logic.
- - registers for the integrated I2C master controller.
- - look-up table RAM for voltage register values.
-- interrupts: Should contain the DFLL block interrupt.
-- clocks: Must contain an entry for each entry in clock-names.
- See clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - soc: Clock source for the DFLL control logic.
- - ref: The closed loop reference clock
- - i2c: Clock source for the integrated I2C master.
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - dvco: Reset control for the DFLL DVCO.
-- #clock-cells: Must be 0.
-- clock-output-names: Name of the clock output.
-- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
- hardware will start controlling. The regulator will be queried for
- the I2C register, control values and supported voltages.
-
-Required properties for the control loop parameters:
-- nvidia,sample-rate: Sample rate of the DFLL control loop.
-- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
-- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
-- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
-- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
-- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
-
-Optional properties for the control loop parameters:
-- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
-
-Optional properties for mode selection:
-- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
-
-Required properties for I2C mode:
-- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
-
-Required properties for PWM mode:
-- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
-- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
- control is disabled and the PWM output is tristated. Note that this voltage is
- configured in hardware, typically via a resistor divider.
-- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
- is enabled and PWM output is low. Hence, this is the minimum output voltage
- that the regulator supports when PWM control is enabled.
-- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
- corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
- duty cycle would be: nvidia,pwm-min-microvolts +
- nvidia,pwm-voltage-step-microvolts * 2.
-- pinctrl-0: I/O pad configuration when PWM control is enabled.
-- pinctrl-1: I/O pad configuration when PWM control is disabled.
-- pinctrl-names: must include the following entries:
- - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
- - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
-
-Example for I2C:
-
-clock@70110000 {
- compatible = "nvidia,tegra124-dfll";
- reg = <0 0x70110000 0 0x100>, /* DFLL control */
- <0 0x70110000 0 0x100>, /* I2C output control */
- <0 0x70110100 0 0x100>, /* Integrated I2C controller */
- <0 0x70110200 0 0x100>; /* Look-up table RAM */
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
- <&tegra_car TEGRA124_CLK_DFLL_REF>,
- <&tegra_car TEGRA124_CLK_I2C5>;
- clock-names = "soc", "ref", "i2c";
- resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
- reset-names = "dvco";
- #clock-cells = <0>;
- clock-output-names = "dfllCPU_out";
- vdd-cpu-supply = <&vdd_cpu>;
-
- nvidia,sample-rate = <12500>;
- nvidia,droop-ctrl = <0x00000f00>;
- nvidia,force-mode = <1>;
- nvidia,cf = <10>;
- nvidia,ci = <0>;
- nvidia,cg = <2>;
-
- nvidia,i2c-fs-rate = <400000>;
-};
-
-Example for PWM:
-
-clock@70110000 {
- compatible = "nvidia,tegra124-dfll";
- reg = <0 0x70110000 0 0x100>, /* DFLL control */
- <0 0x70110000 0 0x100>, /* I2C output control */
- <0 0x70110100 0 0x100>, /* Integrated I2C controller */
- <0 0x70110200 0 0x100>; /* Look-up table RAM */
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
- <&tegra_car TEGRA210_CLK_DFLL_REF>,
- <&tegra_car TEGRA124_CLK_I2C5>;;
- clock-names = "soc", "ref", "i2c";
- resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
- reset-names = "dvco";
- #clock-cells = <0>;
- clock-output-names = "dfllCPU_out";
-
- nvidia,sample-rate = <25000>;
- nvidia,droop-ctrl = <0x00000f00>;
- nvidia,force-mode = <1>;
- nvidia,cf = <6>;
- nvidia,ci = <0>;
- nvidia,cg = <2>;
-
- nvidia,pwm-min-microvolts = <708000>; /* 708mV */
- nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
- nvidia,pwm-to-pmic;
- nvidia,pwm-tristate-microvolts = <1000000>;
- nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
-
- pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
- pinctrl-0 = <&dvfs_pwm_active_state>;
- pinctrl-1 = <&dvfs_pwm_inactive_state>;
-};
-
-/* pinmux nodes added for completeness. Binding doc can be found in:
- * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
- */
-
-pinmux: pinmux@700008d4 {
- dvfs_pwm_active_state: dvfs_pwm_active {
- dvfs_pwm_pbb1 {
- nvidia,pins = "dvfs_pwm_pbb1";
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
- };
- dvfs_pwm_inactive_state: dvfs_pwm_inactive {
- dvfs_pwm_pbb1 {
- nvidia,pins = "dvfs_pwm_pbb1";
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
new file mode 100644
index 000000000000..5d689e48c438
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
@@ -0,0 +1,290 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description:
+ The DFLL IP block on Tegra is a root clocksource designed for clocking
+ the fast CPU cluster. It consists of a free-running voltage controlled
+ oscillator connected to the CPU voltage rail (VDD_CPU), and a closed
+ loop control module that will automatically adjust the VDD_CPU voltage
+ by communicating with an off-chip PMIC either via an I2C bus or via
+ PWM signals.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra124-dfll
+ - nvidia,tegra210-dfll
+
+ reg:
+ items:
+ - description: DFLL control logic
+ - description: I2C output logic
+ - description: Integrated I2C controller
+ - description: Look-up table RAM for voltage register values
+
+ interrupts:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: Clock source for the DFLL control logic
+ - description: Closed loop reference clock
+ - description: Clock source for the integrated I2C controller
+
+ clock-names:
+ items:
+ - const: soc
+ - const: ref
+ - const: i2c
+
+ clock-output-names:
+ description: Name of the clock output
+ items:
+ - const: dfllCPU_out
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: dvco
+ - const: dfll
+
+ vdd-cpu-supply:
+ description: Regulator for the CPU voltage rail that the DFLL
+ hardware will start controlling. The regulator will be queried for
+ the I2C register, control values and supported voltages.
+
+ nvidia,sample-rate:
+ description: Sample rate of the DFLL control loop
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 12500
+ maximum: 25000
+
+ nvidia,droop-ctrl:
+ description: Droop control parameter (CL_DVFS_DROOP_CTRL) in the TRM
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ nvidia,force-mode:
+ description: See the field DFLL_PARAMS_FORCE_MODE in the TRM
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: disabled
+ const: 0
+ - description: fixed delay mode
+ const: 1
+ - description: auto mode
+ const: 2
+
+ nvidia,cf:
+ description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 63
+
+ nvidia,ci:
+ description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+
+ nvidia,cg:
+ description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+
+ # optional properties
+ nvidia,cg-scale:
+ description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ nvidia,pwm-to-pmic:
+ description: Use PWM to control regulator rather than I2C
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ nvidia,i2c-fs-rate:
+ description: I2C transfer rate, if using full speed mode
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [100000, 400000]
+
+ # required properties for PWM mode
+ nvidia,pwm-period-nanoseconds:
+ description: Period of PWM square wave in nanoseconds
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1000
+ maximum: 1000000000
+
+ nvidia,pwm-tristate-microvolts:
+ description: Regulator voltage in microvolts when PWM control is disabled
+ and the PWM output is tristated. Note that this voltage is configured in
+ hardware, typically via a resistor divider.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ nvidia,pwm-min-microvolts:
+ description: Regulator voltage in microvolts when PWM control is enabled
+ and PWM output is low. Hence, this is the minimum output voltage that
+ the regulator supports when PWM control is enabled.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3300000
+
+ nvidia,pwm-voltage-step-microvolts:
+ description: |
+ Voltage increase in micro volts corresponding to a 1/33th increase
+ in duty cycle. For example, the voltage for 2/33th duty cycle would be:
+
+ nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 100000
+
+ pinctrl-0:
+ description: I/O pad configuration when PWM control is enabled
+
+ pinctrl-1:
+ description: I/O pad configuration when PWM control is disabled
+
+ pinctrl-names:
+ items:
+ - const: dvfs_pwm_enable
+ - const: dvfs_pwm_disable
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - clock-output-names
+ - resets
+ - reset-names
+ - nvidia,sample-rate
+ - nvidia,droop-ctrl
+ - nvidia,force-mode
+ - nvidia,cf
+ - nvidia,ci
+ - nvidia,cg
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra124-dfll
+ then:
+ properties:
+ resets:
+ maxItems: 1
+
+ reset-names:
+ maxItems: 1
+ else:
+ properties:
+ resets:
+ minItems: 2
+
+ reset-names:
+ minItems: 2
+
+ - if:
+ required:
+ - nvidia,pwm-to-pmic
+ then:
+ required:
+ - nvidia,pwm-min-microvolts
+ - nvidia,pwm-period-nanoseconds
+ - nvidia,pwm-tristate-microvolts
+ - nvidia,pwm-voltage-step-microvolts
+ else:
+ required:
+ - vdd-cpu-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/tegra124-car.h>
+
+ clock@70110000 {
+ compatible = "nvidia,tegra124-dfll";
+ reg = <0x70110000 0x100>, /* DFLL control */
+ <0x70110000 0x100>, /* I2C output control */
+ <0x70110100 0x100>, /* Integrated I2C controller */
+ <0x70110200 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA124_CLK_DFLL_REF>,
+ <&tegra_car TEGRA124_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ vdd-cpu-supply = <&vdd_cpu>;
+
+ nvidia,sample-rate = <12500>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <10>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+
+ nvidia,i2c-fs-rate = <400000>;
+ };
+
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/tegra210-car.h>
+
+ clock@70110000 {
+ compatible = "nvidia,tegra210-dfll";
+ reg = <0x70110000 0x100>, /* DFLL control */
+ <0x70110000 0x100>, /* I2C output control */
+ <0x70110100 0x100>, /* Integrated I2C controller */
+ <0x70110200 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA210_CLK_DFLL_REF>,
+ <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
+ <&tegra_car 155>;
+ reset-names = "dvco", "dfll";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ vdd-cpu-supply = <&vdd_cpu>;
+
+ nvidia,sample-rate = <25000>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <6>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+
+ nvidia,pwm-min-microvolts = <708000>; /* 708mV */
+ nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+ nvidia,pwm-to-pmic;
+ nvidia,pwm-tristate-microvolts = <1000000>;
+ nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
+ };
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v3 03/10] dt-bindings: clock: tegra124-dfll: Convert to json-schema
2026-02-23 14:32 ` [PATCH v3 03/10] dt-bindings: clock: tegra124-dfll: " Thierry Reding
@ 2026-03-06 0:22 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2026-03-06 0:22 UTC (permalink / raw)
To: Thierry Reding
Cc: Jon Hunter, devicetree, Conor Dooley, linux-tegra,
Krzysztof Kozlowski
On Mon, 23 Feb 2026 15:32:58 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra124 (and later) DFLL bindings from the free-form text
> format to json-schema.
>
> Co-developed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v3:
> - adopt some changes from Rob's patch
> - turn dependencies into if:then:else to correctly represent when
> the vdd-cpu-supply property is needed
>
> Changes in v2:
> - license under GPL-2.0-only OR BSD-2-Clause
> - add constraints for vendor properties
>
> .../bindings/clock/nvidia,tegra124-dfll.txt | 155 ----------
> .../bindings/clock/nvidia,tegra124-dfll.yaml | 290 ++++++++++++++++++
> 2 files changed, 290 insertions(+), 155 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 04/10] dt-bindings: interrupt-controller: tegra: Fix reg entries
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (2 preceding siblings ...)
2026-02-23 14:32 ` [PATCH v3 03/10] dt-bindings: clock: tegra124-dfll: " Thierry Reding
@ 2026-02-23 14:32 ` Thierry Reding
2026-03-06 0:23 ` Rob Herring (Arm)
2026-02-23 14:33 ` [PATCH v2 05/10] dt-bindings: arm: tegra: Add missing compatible strings Thierry Reding
` (6 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30
which supports only 5 entries.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../nvidia,tegra20-ictlr.yaml | 23 +++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml
index 074a873880e5..d0c039d14ad2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.yaml
@@ -35,11 +35,12 @@ properties:
- enum:
- nvidia,tegra20-ictlr
- nvidia,tegra30-ictlr
+ - nvidia,tegra210-ictlr
reg:
description: Each entry is a block of 32 interrupts
minItems: 4
- maxItems: 5
+ maxItems: 6
interrupt-controller: true
@@ -64,10 +65,28 @@ allOf:
properties:
reg:
maxItems: 4
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra30-ictlr
+ then:
properties:
reg:
minItems: 5
+ maxItems: 5
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra210-ictlr
+ then:
+ properties:
+ reg:
+ minItems: 6
+ maxItems: 6
examples:
- |
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 04/10] dt-bindings: interrupt-controller: tegra: Fix reg entries
2026-02-23 14:32 ` [PATCH 04/10] dt-bindings: interrupt-controller: tegra: Fix reg entries Thierry Reding
@ 2026-03-06 0:23 ` Rob Herring (Arm)
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring (Arm) @ 2026-03-06 0:23 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-tegra, Conor Dooley, Jon Hunter, Krzysztof Kozlowski,
devicetree
On Mon, 23 Feb 2026 15:32:59 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30
> which supports only 5 entries.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../nvidia,tegra20-ictlr.yaml | 23 +++++++++++++++++--
> 1 file changed, 21 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 05/10] dt-bindings: arm: tegra: Add missing compatible strings
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (3 preceding siblings ...)
2026-02-23 14:32 ` [PATCH 04/10] dt-bindings: interrupt-controller: tegra: Fix reg entries Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-02-23 14:33 ` [PATCH 06/10] dt-bindings: phy: tegra: Document Tegra210 USB PHY Thierry Reding
` (5 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra, Krzysztof Kozlowski
From: Thierry Reding <treding@nvidia.com>
The Nyan Blaze and Nyan Big, as well as Jetson Nano (P3450-0000), Darcy
(P2894-0050-A08) and Pixel C (Smaug) were never mentioned. Add them.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- drop comment about Toradex Apalis typofix, that was already fixed in a
separate patch
.../devicetree/bindings/arm/tegra.yaml | 51 +++++++++++++++++--
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml
index 50a31dba7bec..07e225a4d69b 100644
--- a/Documentation/devicetree/bindings/arm/tegra.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra.yaml
@@ -131,6 +131,33 @@ properties:
- const: toradex,apalis-tk1-v1.2
- const: toradex,apalis-tk1
- const: nvidia,tegra124
+ - items:
+ - const: google,nyan-big-rev7
+ - const: google,nyan-big-rev6
+ - const: google,nyan-big-rev5
+ - const: google,nyan-big-rev4
+ - const: google,nyan-big-rev3
+ - const: google,nyan-big-rev2
+ - const: google,nyan-big-rev1
+ - const: google,nyan-big-rev0
+ - const: google,nyan-big
+ - const: google,nyan
+ - const: nvidia,tegra124
+ - items:
+ - const: google,nyan-blaze-rev10
+ - const: google,nyan-blaze-rev9
+ - const: google,nyan-blaze-rev8
+ - const: google,nyan-blaze-rev7
+ - const: google,nyan-blaze-rev6
+ - const: google,nyan-blaze-rev5
+ - const: google,nyan-blaze-rev4
+ - const: google,nyan-blaze-rev3
+ - const: google,nyan-blaze-rev2
+ - const: google,nyan-blaze-rev1
+ - const: google,nyan-blaze-rev0
+ - const: google,nyan-blaze
+ - const: google,nyan
+ - const: nvidia,tegra124
- items:
- enum:
- nvidia,norrin
@@ -184,17 +211,35 @@ properties:
- const: nvidia,tegra124
- items:
- enum:
- - nvidia,darcy
- nvidia,p2371-0000
- nvidia,p2371-2180
- nvidia,p2571
- - nvidia,p2894-0050-a08
- - nvidia,p3450-0000
- const: nvidia,tegra210
- items:
- const: nvidia,p3541-0000
- const: nvidia,p3450-0000
- const: nvidia,tegra210
+ - description: NVIDIA Jetson Nano
+ items:
+ - const: nvidia,p3450-0000
+ - const: nvidia,tegra210
+ - description: NVIDIA Shield TV
+ items:
+ - const: nvidia,p2894-0050-a08
+ - const: nvidia,darcy
+ - const: nvidia,tegra210
+ - description: Google Pixel C
+ items:
+ - const: google,smaug-rev8
+ - const: google,smaug-rev7
+ - const: google,smaug-rev6
+ - const: google,smaug-rev5
+ - const: google,smaug-rev4
+ - const: google,smaug-rev3
+ - const: google,smaug-rev2
+ - const: google,smaug-rev1
+ - const: google,smaug
+ - const: nvidia,tegra210
- description: Jetson TX2 Developer Kit
items:
- const: nvidia,p2771-0000
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 06/10] dt-bindings: phy: tegra: Document Tegra210 USB PHY
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (4 preceding siblings ...)
2026-02-23 14:33 ` [PATCH v2 05/10] dt-bindings: arm: tegra: Add missing compatible strings Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-03-06 0:23 ` Rob Herring (Arm)
2026-02-23 14:33 ` [PATCH v2 07/10] dt-bindings: memory: Add Tegra210 memory controller bindings Thierry Reding
` (4 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add a compatible string for the USB PHY found on Tegra210 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
index d61585c96e31..a37e8322dc50 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
@@ -16,6 +16,7 @@ properties:
oneOf:
- items:
- enum:
+ - nvidia,tegra210-usb-phy
- nvidia,tegra124-usb-phy
- nvidia,tegra114-usb-phy
- enum:
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 07/10] dt-bindings: memory: Add Tegra210 memory controller bindings
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (5 preceding siblings ...)
2026-02-23 14:33 ` [PATCH 06/10] dt-bindings: phy: tegra: Document Tegra210 USB PHY Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-03-06 0:25 ` Rob Herring
2026-02-23 14:33 ` [PATCH 08/10] dt-bindings: memory: tegra210: Mark EMC as cooling device Thierry Reding
` (3 subsequent siblings)
10 siblings, 1 reply; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Document the bindings for the memory controller found on Tegra210 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- drop unneeded node alias
.../nvidia,tegra210-mc.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
new file mode 100644
index 000000000000..7f003fc422ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra210 SoC Memory Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: |
+ The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split into two 32 bit
+ channels to support LPDDR3 and LPDDR4 with x16 subpartitions. The MC handles memory requests for
+ 34-bit virtual addresses from internal clients and arbitrates among them to allocate memory
+ bandwidth.
+
+ Up to 8 GiB of physical memory can be supported. Security features such as encryption of traffic
+ to and from DRAM via general security apertures are available for video and other secure
+ applications.
+
+properties:
+ $nodename:
+ pattern: "^memory-controller@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - nvidia,tegra210-mc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names:
+ items:
+ - const: mc
+
+ "#iommu-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#iommu-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra210-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ memory-controller@70019000 {
+ compatible = "nvidia,tegra210-mc";
+ reg = <0x70019000 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_MC>;
+ clock-names = "mc";
+
+ #iommu-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 07/10] dt-bindings: memory: Add Tegra210 memory controller bindings
2026-02-23 14:33 ` [PATCH v2 07/10] dt-bindings: memory: Add Tegra210 memory controller bindings Thierry Reding
@ 2026-03-06 0:25 ` Rob Herring
0 siblings, 0 replies; 19+ messages in thread
From: Rob Herring @ 2026-03-06 0:25 UTC (permalink / raw)
To: Thierry Reding
Cc: Krzysztof Kozlowski, Conor Dooley, Jon Hunter, devicetree,
linux-tegra
On Mon, Feb 23, 2026 at 03:33:02PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Document the bindings for the memory controller found on Tegra210 SoCs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - drop unneeded node alias
>
> .../nvidia,tegra210-mc.yaml | 77 +++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> new file mode 100644
> index 000000000000..7f003fc422ab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra210 SoC Memory Controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +description: |
> + The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split into two 32 bit
> + channels to support LPDDR3 and LPDDR4 with x16 subpartitions. The MC handles memory requests for
> + 34-bit virtual addresses from internal clients and arbitrates among them to allocate memory
> + bandwidth.
> +
> + Up to 8 GiB of physical memory can be supported. Security features such as encryption of traffic
> + to and from DRAM via general security apertures are available for video and other secure
> + applications.
Wrap lines at 80.
Otherwise,
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 08/10] dt-bindings: memory: tegra210: Mark EMC as cooling device
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (6 preceding siblings ...)
2026-02-23 14:33 ` [PATCH v2 07/10] dt-bindings: memory: Add Tegra210 memory controller bindings Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-02-23 14:33 ` [PATCH 09/10] arm64: tegra: Fix snps,blen properties Thierry Reding
` (2 subsequent siblings)
10 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The external memory controller found on Tegra210 can use throttling of
the EMC frequency in order to reduce the memory chip temperature. Mark
the memory controller as a cooling device to take advantage of this
functionality.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/memory-controllers/nvidia,tegra210-emc.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
index 4e4fb4acd7f9..7a653a011f03 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -52,6 +52,9 @@ properties:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
+allOf:
+ - $ref: /schemas/thermal/thermal-cooling-devices.yaml
+
required:
- compatible
- reg
@@ -59,7 +62,7 @@ required:
- clock-names
- nvidia,memory-controller
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -90,4 +93,5 @@ examples:
operating-points-v2 = <&dvfs_opp_table>;
#interconnect-cells = <0>;
+ #cooling-cells = <2>;
};
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 09/10] arm64: tegra: Fix snps,blen properties
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (7 preceding siblings ...)
2026-02-23 14:33 ` [PATCH 08/10] dt-bindings: memory: tegra210: Mark EMC as cooling device Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-02-23 14:33 ` [PATCH 10/10] arm64: tegra: Drop redundant clock and reset names for TSEC Thierry Reding
2026-02-23 17:11 ` [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Rob Herring
10 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The snps,blen property of stmmac-axi-config nodes needs to have 7
entries in total, with unsupported burst lengths listed as 0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 13ec999e52ef..4ae3601734d0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -3621,7 +3621,7 @@ ethernet@6800000 {
snps,axi-config = <&mgbe0_axi_setup>;
mgbe0_axi_setup: stmmac-axi-config {
- snps,blen = <256 128 64 32>;
+ snps,blen = <256 128 64 32 0 0 0>;
snps,rd_osr_lmt = <63>;
snps,wr_osr_lmt = <63>;
};
@@ -3663,7 +3663,7 @@ ethernet@6900000 {
snps,axi-config = <&mgbe1_axi_setup>;
mgbe1_axi_setup: stmmac-axi-config {
- snps,blen = <256 128 64 32>;
+ snps,blen = <256 128 64 32 0 0 0>;
snps,rd_osr_lmt = <63>;
snps,wr_osr_lmt = <63>;
};
@@ -3705,7 +3705,7 @@ ethernet@6a00000 {
snps,axi-config = <&mgbe2_axi_setup>;
mgbe2_axi_setup: stmmac-axi-config {
- snps,blen = <256 128 64 32>;
+ snps,blen = <256 128 64 32 0 0 0>;
snps,rd_osr_lmt = <63>;
snps,wr_osr_lmt = <63>;
};
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 10/10] arm64: tegra: Drop redundant clock and reset names for TSEC
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (8 preceding siblings ...)
2026-02-23 14:33 ` [PATCH 09/10] arm64: tegra: Fix snps,blen properties Thierry Reding
@ 2026-02-23 14:33 ` Thierry Reding
2026-02-23 17:11 ` [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Rob Herring
10 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2026-02-23 14:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding
Cc: Jon Hunter, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The DT bindings don't allow the clock and reset names to be specified
since there is only a single entry for each.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 137aa8375257..5f5e5370d709 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -309,9 +309,7 @@ tsec@54500000 {
reg = <0x0 0x54500000 0x0 0x00040000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSECB>;
- clock-names = "tsec";
resets = <&tegra_car 206>;
- reset-names = "tsec";
status = "disabled";
};
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings
2026-02-23 14:32 [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Thierry Reding
` (9 preceding siblings ...)
2026-02-23 14:33 ` [PATCH 10/10] arm64: tegra: Drop redundant clock and reset names for TSEC Thierry Reding
@ 2026-02-23 17:11 ` Rob Herring
2026-02-27 12:03 ` Thierry Reding
10 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2026-02-23 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Krzysztof Kozlowski, Conor Dooley, Jon Hunter, devicetree,
linux-tegra
On Mon, Feb 23, 2026 at 03:32:55PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> This patch set contains a couple of cleanups and conversions for Tegra-
> related bindings. In total, on top of next-20260220, these patches get
> the number of DT validation issues down from 184 to just 88.
Great! Really, you were at only 40 unique warnings (I strip the
filenames to avoid multiple boards duplicating warnings). You're in 4th
(to last) place:
arch/arm64/boot/dts/hisilicon:116:74
arch/arm64/boot/dts/mediatek:197:48
arch/arm64/boot/dts/qcom:132:45
arch/arm64/boot/dts/nvidia:184:40
arch/arm64/boot/dts/rockchip:76:27
arch/arm64/boot/dts/marvell:182:23
arch/arm64/boot/dts/renesas:83:13
arch/arm64/boot/dts/xilinx:16:6
arch/arm64/boot/dts/microchip:22:6
arch/arm64/boot/dts/broadcom:32:4
arch/arm64/boot/dts/nuvoton:3:3
arch/arm64/boot/dts/sprd:2:2
arch/arm64/boot/dts/intel:2:2
arch/arm64/boot/dts/apm:3:2
arch/arm64/boot/dts/realtek:45:1
arch/arm64/boot/dts/freescale:2:1
arch/arm64/boot/dts/arm:1:1
This and logs of all the warnings from next and Linus' trees can be
retrieved with scripts here:
https://gitlab.com/robherring/ci-jobs
> Note that technically these are at different revisions because they had
> been sent out separately a while ago, Some of these have already been
> reviewed, but given that they are fairly old I wanted to send them out
> in case there are new best practices that these don't include. I've run
> all of these through dt_binding_check. Also I've verified that these do
> not produce any new warnings/errors while eliminating old ones.
>
> Krzysztof, Rob, I know that you prefer DT binding changes to go through
> driver trees, but given that these don't have any driver changes to go
> with them, should we queue these via the Tegra tree (or devicetree tree)
> once they've passed review?
I prefer they go via subsystem trees still, but if you don't get a reply
in reasonable time just take them. You can take the interrupt-controller
one though as DT only changes don't tend to get picked up.
> I plan to pick up the two DTS changes into the Tegra tree since they are
> fairly trivial and unrelated to the bindings changes. I suppose they
> could've just been a separate series, but I thought I'd post them along
> with the other changes since this is all a concerted effort to get the
> number of issues down.
>
> Thanks,
> Thierry
>
> Thierry Reding (10):
> dt-bindings: phy: tegra-xusb: Document Type C support
> dt-bindings: pci: tegra: Convert to json-schema
> dt-bindings: clock: tegra124-dfll: Convert to json-schema
> dt-bindings: interrupt-controller: tegra: Fix reg entries
> dt-bindings: arm: tegra: Add missing compatible strings
> dt-bindings: phy: tegra: Document Tegra210 USB PHY
> dt-bindings: memory: Add Tegra210 memory controller bindings
> dt-bindings: memory: tegra210: Mark EMC as cooling device
> arm64: tegra: Fix snps,blen properties
> arm64: tegra: Drop redundant clock and reset names for TSEC
arm64: dts: tegra: ...
Rob
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings
2026-02-23 17:11 ` [PATCH 00/10] dt-bindings: Various cleanups for Tegra-related bindings Rob Herring
@ 2026-02-27 12:03 ` Thierry Reding
0 siblings, 0 replies; 19+ messages in thread
From: Thierry Reding @ 2026-02-27 12:03 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Conor Dooley, Jon Hunter, devicetree,
linux-tegra
[-- Attachment #1: Type: text/plain, Size: 4155 bytes --]
On Mon, Feb 23, 2026 at 11:11:40AM -0600, Rob Herring wrote:
> On Mon, Feb 23, 2026 at 03:32:55PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > This patch set contains a couple of cleanups and conversions for Tegra-
> > related bindings. In total, on top of next-20260220, these patches get
> > the number of DT validation issues down from 184 to just 88.
Hi Rob,
sorry for the late reply. I've recently switched to the kernel.org
address and for some reason these messages now don't show up in my
inbox and I only see them on the lore archives.
> Great! Really, you were at only 40 unique warnings (I strip the
> filenames to avoid multiple boards duplicating warnings). You're in 4th
> (to last) place:
>
> arch/arm64/boot/dts/hisilicon:116:74
> arch/arm64/boot/dts/mediatek:197:48
> arch/arm64/boot/dts/qcom:132:45
> arch/arm64/boot/dts/nvidia:184:40
> arch/arm64/boot/dts/rockchip:76:27
> arch/arm64/boot/dts/marvell:182:23
> arch/arm64/boot/dts/renesas:83:13
> arch/arm64/boot/dts/xilinx:16:6
> arch/arm64/boot/dts/microchip:22:6
> arch/arm64/boot/dts/broadcom:32:4
> arch/arm64/boot/dts/nuvoton:3:3
> arch/arm64/boot/dts/sprd:2:2
> arch/arm64/boot/dts/intel:2:2
> arch/arm64/boot/dts/apm:3:2
> arch/arm64/boot/dts/realtek:45:1
> arch/arm64/boot/dts/freescale:2:1
> arch/arm64/boot/dts/arm:1:1
\o/ ... I guess...
I've got a bunch more that I plan to flush out. Hopefully I can make a
bit quicker progress this time around.
> This and logs of all the warnings from next and Linus' trees can be
> retrieved with scripts here:
>
> https://gitlab.com/robherring/ci-jobs
>
>
> > Note that technically these are at different revisions because they had
> > been sent out separately a while ago, Some of these have already been
> > reviewed, but given that they are fairly old I wanted to send them out
> > in case there are new best practices that these don't include. I've run
> > all of these through dt_binding_check. Also I've verified that these do
> > not produce any new warnings/errors while eliminating old ones.
> >
> > Krzysztof, Rob, I know that you prefer DT binding changes to go through
> > driver trees, but given that these don't have any driver changes to go
> > with them, should we queue these via the Tegra tree (or devicetree tree)
> > once they've passed review?
>
> I prefer they go via subsystem trees still, but if you don't get a reply
> in reasonable time just take them. You can take the interrupt-controller
> one though as DT only changes don't tend to get picked up.
Is this an implied "Reviewed-by"? Some of these have been reviewed, but
some were either not sent out yet, or didn't get any response at the
time?
> > I plan to pick up the two DTS changes into the Tegra tree since they are
> > fairly trivial and unrelated to the bindings changes. I suppose they
> > could've just been a separate series, but I thought I'd post them along
> > with the other changes since this is all a concerted effort to get the
> > number of issues down.
> >
> > Thanks,
> > Thierry
> >
> > Thierry Reding (10):
> > dt-bindings: phy: tegra-xusb: Document Type C support
> > dt-bindings: pci: tegra: Convert to json-schema
> > dt-bindings: clock: tegra124-dfll: Convert to json-schema
> > dt-bindings: interrupt-controller: tegra: Fix reg entries
> > dt-bindings: arm: tegra: Add missing compatible strings
> > dt-bindings: phy: tegra: Document Tegra210 USB PHY
> > dt-bindings: memory: Add Tegra210 memory controller bindings
> > dt-bindings: memory: tegra210: Mark EMC as cooling device
> > arm64: tegra: Fix snps,blen properties
> > arm64: tegra: Drop redundant clock and reset names for TSEC
>
> arm64: dts: tegra: ...
How strong is the suggestion? We've used just "arm64: tegra:" since
basically forever. I can obviously switch at some point, but it'll be a
break in consistency. Although, looking at the logs for the last few
years, there have been occasional arm64: dts: tegra prefixes and a
(very) few outliers with totally butchered prefixes.
Thierry
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^ permalink raw reply [flat|nested] 19+ messages in thread