[PATCH 1/1] PCI: tegra194: fix min() signedness when capping ASPM L1 entrance latency

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

The DT property "aspm-l1-entry-delay-ns" is converted to microseconds,
then encoded for the L1 entrance latency register field as ilog2(us) + 1,
clamped to the hardware maximum of 7.

ilog2() returns int type, while the upper bound is 7U (unsigned int).
The min() macro is implemented with __careful_cmp(), which rejects mixed
signed and unsigned operands at compile time via BUILD_BUG_ON_MSG in
minmax.h; that check trips on this pair, notably when building with W=1.

This combination fails to build (e.g. parisc allyesconfig, GCC 15, as
reported by the 0-day bot).

Use min_t(u32, ilog2(us) + 1U, 7U) so both sides of the comparison are
unsigned and consistent with aspm_l1_enter_lat.

Fixes: 4a44cd65c9dd ("PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency")
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202604051407.AODe3ddZ-lkp@intel.com/
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 393f75ce3df3..93d3452ac117 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1147,7 +1147,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 	if (!ret) {
 		u32 us = max(val / 1000, 1U);
 
-		pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7U);
+		pcie->aspm_l1_enter_lat = min_t(u32, ilog2(us) + 1U, 7U);
 	}
 
 	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
-- 
2.34.1