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Thu, 16 Apr 2026 04:51:38 -0700 From: Kartik Rajput To: Thierry Reding , Jonathan Hunter , Christophe Leroy , Jiri Slaby , Prathamesh Shete , , CC: Kartik Rajput Subject: [PATCH v3] soc/tegra: pmc: Add PMC support for Tegra410 Date: Thu, 16 Apr 2026 17:21:34 +0530 Message-ID: <20260416115134.1032155-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|IA0PR12MB8906:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c3df78c-b8cd-49fa-b8ca-08de9bae8d03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 4py77gEerzsKqX2nE+vOBNuglVTit24BgYSePEWoHJaodwz7VshQ9FhwgIwVtxUFSDzB57lEgSXbAm5SSs6iuJAgE9YSGH2ZH2wPS5KJ5mthxdSPKomT5HQb9O7cNtgJST2RxaN8chPEww/j1sz1VpKPd6UxsKeiNONu9Fq0QXLLI8YG3URRMyGt/qU4ScnAclag7fG1i2CNih7xhw+Jxv4eLFKNqUaPpzHDhV6NxiuxkHqdNJAMowEKCyTy/hnkT2Uf2gELLIsUKUZYbJtypaE4tzrl/BL7wlHHN4SwdCZ13PCCHCTQoqI7IMNCEzZofPpY8BwM/9knSFdsUzyRIYg+ArMvzwckoUmIYXsWnQe+bMpFCgAuI/cLqALe+ybwlUribzgH2nsPjSd/ct40vLPxxd1GfTF9QB5fe9GxpyWBHI+cHISC044QxfnlIzumbqqrcPab+yATwbugLQTotVqhpOuMihOzmtMZ2toitD/JSukVef4dmvtN3ep+HlymAyHMxZJU1gp8Kb7xZp2Tdjn6BNHphkZYdnRNPDqjVomb23+ZyCCHy5/Zj7qgpX+CvLidb5piuBjgxzVZbQCRhkjVUJLtbGgNzJ4A1N2H62TbtNOoWr05mMsSDM3EYoo8PQUPvGCRMY5kYxPpCkhsI0NO5mOO8sc8qVI4i4HXL5p+z3pIY6lVRu8AfQ7XtjhnW4ubEXFH+XyEGed8FyloDzljDjc9xDbgjMTPe9r4ibfBQFafJ1nKD9uoipc3+5SaWUe69OHgDKPjK5ceHtmG5Q== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0/llqmI2zlYaa5zuQUSIGhE2P08FOxlIC8jH1zJ+TtH+JizADOAnjeBw+RTANbg4ZIYW2YSjWpAXn9XDZcWb5rWiRmu7kEec1CTAGrb6O9vLRhexm24nFa82oT7W/7j8BCndMX7EIfiEzNaI+6OsQBEtOMYLEn1/gr799dhUxw+f8q5hTyE+ECARW7IsxHMrGWOs+KatY7VCt2LaLsetBG0iuMDzER0T1sspA/ZJiANJT0WiconUT2yXUK2Q03pc5mJuK3ufK7WmSEFOGiLpP/lfR8522Yd/YOOr5KsgYZruHKOoocPnIuLjXiFhw3KsE7RQVoL2THRp1t/an/4L6pp9tcCcFHnYUEUx21PxS0COtdCCgosbxpG8B8MgjDbxa6EuueEsJTh3qlVo+eAankPfPZpOljQPEbHc6qs3/27T9us16ySWMTDP8ePD0UiO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2026 11:51:52.4238 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c3df78c-b8cd-49fa-b8ca-08de9bae8d03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8906 Tegra410 uses PMC driver only to retrieve system reset reason using PMC sysfs. Tegra410 uses ACPI to probe PMC, unlike device-tree boot it does not use the early initialisation sequence. Add PMC support for Tegra410, which uses the PMC driver to retrieve the system reset reason via PMC sysfs. Signed-off-by: Kartik Rajput --- Changes in v3: * Remove unused entries from tegra410_pmc_soc. Changes in v2: * Updated commit message. --- drivers/soc/tegra/pmc.c | 101 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2ee6539d796a..f89de1969946 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "tegra-pmc: " fmt +#include #include #include #include @@ -3117,12 +3118,30 @@ static void tegra_pmc_reset_suspend_mode(void *data) pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; } +static int tegra_pmc_acpi_probe(struct platform_device *pdev) +{ + pmc->soc = device_get_match_data(&pdev->dev); + pmc->dev = &pdev->dev; + + pmc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmc->base)) + return PTR_ERR(pmc->base); + + tegra_pmc_reset_sysfs_init(pmc); + platform_set_drvdata(pdev, pmc); + + return 0; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base; struct resource *res; int err; + if (is_acpi_node(dev_fwnode(&pdev->dev))) + return tegra_pmc_acpi_probe(pdev); + /* * Early initialisation should have configured an initial * register mapping and setup the soc data pointer. If these @@ -4783,6 +4802,81 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = { .max_wake_vectors = 4, }; +static const char * const tegra410_reset_sources[] = { + "SYS_RESET_N", /* 0x0 */ + "CSDC_RTC_XTAL", + "VREFRO_POWER_BAD", + "FMON_32K", + "FMON_OSC", + "POD_RTC", + "POD_IO", + "POD_PLUS_IO_SPLL", + "POD_PLUS_IO_VMON", /* 0x8 */ + "POD_PLUS_SOC", + "VMON_PLUS_UV", + "VMON_PLUS_OV", + "FUSECRC_FAULT", + "OSC_FAULT", + "BPMP_BOOT_FAULT", + "SCPM_BPMP_CORE_CLK", + "SCPM_PSC_SE_CLK", /* 0x10 */ + "VMON_SOC_MIN", + "VMON_SOC_MAX", + "NVJTAG_SEL_MONITOR", + "L0_RST_REQ_N", + "NV_THERM_FAULT", + "PSC_SW", + "POD_C2C_LPI_0", + "POD_C2C_LPI_1", /* 0x18 */ + "BPMP_FMON", + "FMON_SPLL_OUT", + "L1_RST_REQ_N", + "OCP_RECOVERY", + "AO_WDT_POR", + "BPMP_WDT_POR", + "RAS_WDT_POR", + "TOP_0_WDT_POR", /* 0x20 */ + "TOP_1_WDT_POR", + "TOP_2_WDT_POR", + "PSC_WDT_POR", + "OOBHUB_WDT_POR", + "MSS_SEQ_WDT_POR", + "SW_MAIN", + "L0L1_RST_OUT_N", + "HSM", /* 0x28 */ + "CSITE_SW", + "AO_WDT_DBG", + "BPMP_WDT_DBG", + "RAS_WDT_DBG", + "TOP_0_WDT_DBG", + "TOP_1_WDT_DBG", + "TOP_2_WDT_DBG", + "PSC_WDT_DBG", /* 0x30 */ + "TSC_0_WDT_DBG", + "TSC_1_WDT_DBG", + "OOBHUB_WDT_DBG", + "MSS_SEQ_WDT_DBG", + "L2_RST_REQ_N", + "L2_RST_OUT_N", + "SC7" +}; + +static const struct tegra_pmc_regs tegra410_pmc_regs = { + .rst_status = 0x8, + .rst_source_shift = 0x2, + .rst_source_mask = 0xfc, + .rst_level_shift = 0x0, + .rst_level_mask = 0x3, +}; + +static const struct tegra_pmc_soc tegra410_pmc_soc = { + .regs = &tegra410_pmc_regs, + .reset_sources = tegra410_reset_sources, + .num_reset_sources = ARRAY_SIZE(tegra410_reset_sources), + .reset_levels = tegra186_reset_levels, + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), +}; + static const struct of_device_id tegra_pmc_match[] = { { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, @@ -4797,6 +4891,12 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static const struct acpi_device_id tegra_pmc_acpi_match[] = { + { .id = "NVDA2016", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc }, + { } +}; +MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match); + static void tegra_pmc_sync_state(struct device *dev) { struct device_node *np, *child; @@ -4847,6 +4947,7 @@ static struct platform_driver tegra_pmc_driver = { .name = "tegra-pmc", .suppress_bind_attrs = true, .of_match_table = tegra_pmc_match, + .acpi_match_table = tegra_pmc_acpi_match, #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif -- 2.43.0