[PATCH v1 1/1] clk: tegra: support 48MHz clock for pll_p_out1

Svyatoslav Ryhel
2026-04-17T07:37:19Z

From: Dmitry Osipenko <digetx@gmail.com>

UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/clk/tegra/clk-pll.c | 1 +
drivers/clk/tegra/clk-tegra114.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d86003b6d94f..eae732320bec 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -564,6 +564,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
switch (parent_rate) {
case 12000000:
case 26000000:
+ case 48000000:
cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
break;
case 13000000:
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index a4f40533cc43..6a77742aaad2 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -363,13 +363,15 @@ static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
{ 28800000, 282240000, 245, 25, 1, 8 },
{ 28800000, 368640000, 320, 25, 1, 8 },
{ 28800000, 240000000, 200, 24, 1, 8 },
+ { 48000000, 282240000, 147, 25, 1, 8 },
+ { 48000000, 368640000, 192, 25, 1, 8 },
+ { 48000000, 564480000, 294, 25, 1, 8 },
{ 0, 0, 0, 0, 0, 0 },
};

-
static struct tegra_clk_pll_params pll_a_params = {
.input_min = 2000000,
- .input_max = 31000000,
+ .input_max = 48000000,
.cf_min = 1000000,
.cf_max = 6000000,
.vco_min = 200000000,
--
2.51.0