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Wed, 13 May 2026 22:18:48 -0700 From: Kartik Rajput To: , , , , , , CC: Kartik Rajput Subject: [PATCH v3 RESEND] soc/tegra: pmc: Add PMC support for Tegra410 Date: Thu, 14 May 2026 10:48:46 +0530 Message-ID: <20260514051846.2401935-1-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|CYXPR12MB9280:EE_ X-MS-Office365-Filtering-Correlation-Id: f9cd4312-8f8a-4b7f-d336-08deb1785192 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|18002099003|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: LOuyLo41F0Ab33vWF0kaHwQ2v6btbYvxtKdd5mHLR2Tst4QG3c9oiY0scP1OthyHH7zCvp31aSoXu2TkFi2rNTUQwoUCg+w4MPg1AR6MrGKZhqzikxAXwjiH/zxaAHWwSarcOvHM7xvZqiYXWgcIr5Fvr3xLeG7q65gyAk+aqdooWyGMsDiW+poJoSCQjiCVHmgON5e0KZY4vvvznFiuQ0Kx7lz3i4wjdnglpnyeWF0hbyjzGV4fccVE5RUUYXc/S0Yyl10c8bZiwSB2EoAm9V4KDGZiWgAYeqMspV7+1f/XgFAIIrLVBCjH9IjIezzmzgx/8/0F/25WWk4FAm/qW79ceQ3v9jDUSJ+YPaNvciWfWFpDxTNXRPSuy+87q/a1zMbY5lUZaHdVJRI1XmQSUwu9QvMKy+6Xb/n+fYAywcrAJBaklcyUo2ex/FuqF/fwmWnKGo09JwrETGCHXA+wKOc5kSGXKDlgtXgrKTrf0q+GMDiqyqz6/siYClEgAaIuV2xZ+TaUfp0apHsK1mXQ74PwZg9UdNktVYES9Syw9v4Ln/5L0WMtSh4TYb/YafiaiKXkBR8R9Bl8dQ/bAXq2uk0+Sv13e7ep36vNu14bz9N7OkUGAubbCqcOaSJ6dMgqmRc5wuSz+wEAbiJerqx/O5vdk4RznX5s4HZR8s3EZF9J+TOUlyUSJhotNakLsQzJaCz4qZrVhM9Xdt16nix/lPqW4gcHz2xlX5GB7iOi5E8= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(18002099003)(56012099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MvuPKo5iCX60JstxqWs/TWLwgWIe9Nbzesa4C8bf2LWGH4WRFSi1fZIdHxkdseyJgRrW3qysgWlb/HfBWKylvLOcx68rbhBrBlrWhili1v71lyoB1mp5/doTbXrt0+/hyXQPXawel9ZPmvrAKRgNKC2Ow5xIRjkdXGyvicmWLBdzK8Q5wLdSRmSd/hYOXRI3vFOBdAcvkGHXJD8eEIYtTXiMHYfnEJMxgQyobsBcCnC0yxhn1P6vJ+HviacLE8bArtDeVuwP8421RZSh5BVu9SqQShy95+xxRrypmQFsLH23DOfc614vqsJDNdvWcs+mfb+WdRFqeAv4ojYF9HwW+HiwLfUTB9/GxG8WDdRUiqYAXyThJ6DbcYAn3T8MSO90/nQh+67zfM8P0ER94Ho5InZUJZWUA+8uL0ch83CilCI1791FTv3Z/rR2HH/IY4ia X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2026 05:19:05.4601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9cd4312-8f8a-4b7f-d336-08deb1785192 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9280 Tegra410 uses PMC driver only to retrieve system reset reason using PMC sysfs. Tegra410 uses ACPI to probe PMC, unlike device-tree boot it does not use the early initialisation sequence. Add PMC support for Tegra410, which uses the PMC driver to retrieve the system reset reason via PMC sysfs. Signed-off-by: Kartik Rajput --- drivers/soc/tegra/pmc.c | 101 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2ee6539d796a..f89de1969946 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "tegra-pmc: " fmt +#include #include #include #include @@ -3117,12 +3118,30 @@ static void tegra_pmc_reset_suspend_mode(void *data) pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; } +static int tegra_pmc_acpi_probe(struct platform_device *pdev) +{ + pmc->soc = device_get_match_data(&pdev->dev); + pmc->dev = &pdev->dev; + + pmc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmc->base)) + return PTR_ERR(pmc->base); + + tegra_pmc_reset_sysfs_init(pmc); + platform_set_drvdata(pdev, pmc); + + return 0; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base; struct resource *res; int err; + if (is_acpi_node(dev_fwnode(&pdev->dev))) + return tegra_pmc_acpi_probe(pdev); + /* * Early initialisation should have configured an initial * register mapping and setup the soc data pointer. If these @@ -4783,6 +4802,81 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = { .max_wake_vectors = 4, }; +static const char * const tegra410_reset_sources[] = { + "SYS_RESET_N", /* 0x0 */ + "CSDC_RTC_XTAL", + "VREFRO_POWER_BAD", + "FMON_32K", + "FMON_OSC", + "POD_RTC", + "POD_IO", + "POD_PLUS_IO_SPLL", + "POD_PLUS_IO_VMON", /* 0x8 */ + "POD_PLUS_SOC", + "VMON_PLUS_UV", + "VMON_PLUS_OV", + "FUSECRC_FAULT", + "OSC_FAULT", + "BPMP_BOOT_FAULT", + "SCPM_BPMP_CORE_CLK", + "SCPM_PSC_SE_CLK", /* 0x10 */ + "VMON_SOC_MIN", + "VMON_SOC_MAX", + "NVJTAG_SEL_MONITOR", + "L0_RST_REQ_N", + "NV_THERM_FAULT", + "PSC_SW", + "POD_C2C_LPI_0", + "POD_C2C_LPI_1", /* 0x18 */ + "BPMP_FMON", + "FMON_SPLL_OUT", + "L1_RST_REQ_N", + "OCP_RECOVERY", + "AO_WDT_POR", + "BPMP_WDT_POR", + "RAS_WDT_POR", + "TOP_0_WDT_POR", /* 0x20 */ + "TOP_1_WDT_POR", + "TOP_2_WDT_POR", + "PSC_WDT_POR", + "OOBHUB_WDT_POR", + "MSS_SEQ_WDT_POR", + "SW_MAIN", + "L0L1_RST_OUT_N", + "HSM", /* 0x28 */ + "CSITE_SW", + "AO_WDT_DBG", + "BPMP_WDT_DBG", + "RAS_WDT_DBG", + "TOP_0_WDT_DBG", + "TOP_1_WDT_DBG", + "TOP_2_WDT_DBG", + "PSC_WDT_DBG", /* 0x30 */ + "TSC_0_WDT_DBG", + "TSC_1_WDT_DBG", + "OOBHUB_WDT_DBG", + "MSS_SEQ_WDT_DBG", + "L2_RST_REQ_N", + "L2_RST_OUT_N", + "SC7" +}; + +static const struct tegra_pmc_regs tegra410_pmc_regs = { + .rst_status = 0x8, + .rst_source_shift = 0x2, + .rst_source_mask = 0xfc, + .rst_level_shift = 0x0, + .rst_level_mask = 0x3, +}; + +static const struct tegra_pmc_soc tegra410_pmc_soc = { + .regs = &tegra410_pmc_regs, + .reset_sources = tegra410_reset_sources, + .num_reset_sources = ARRAY_SIZE(tegra410_reset_sources), + .reset_levels = tegra186_reset_levels, + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), +}; + static const struct of_device_id tegra_pmc_match[] = { { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, @@ -4797,6 +4891,12 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static const struct acpi_device_id tegra_pmc_acpi_match[] = { + { .id = "NVDA2016", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc }, + { } +}; +MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match); + static void tegra_pmc_sync_state(struct device *dev) { struct device_node *np, *child; @@ -4847,6 +4947,7 @@ static struct platform_driver tegra_pmc_driver = { .name = "tegra-pmc", .suppress_bind_attrs = true, .of_match_table = tegra_pmc_match, + .acpi_match_table = tegra_pmc_acpi_match, #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif -- 2.43.0