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Thu, 14 May 2026 05:49:12 -0700 From: Prathamesh Shete To: Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Thierry Reding , Jonathan Hunter , Prathamesh Shete , , , Subject: [PATCH 2/2] soc/tegra: pmc: Add Tegra238 support Date: Thu, 14 May 2026 12:48:56 +0000 Message-ID: <20260514124856.108606-2-pshete@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260514124856.108606-1-pshete@nvidia.com> References: <20260514124856.108606-1-pshete@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|DM4PR12MB6615:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f52b9da-06b1-4d21-e31e-08deb1b73d58 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|56012099003|22082099003|18002099003|11063799003|3023799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Dhud7fJSyi4b3sljcylb/cprs3xn4fgMJNwDOF4D9CtCRrWQ6QZQugrGJH6FWXgMMID5fJwcgquqYwgNE8EbbpSzAYTwqWtFfD7WikRvJ3CJWj5yGmmnQYA7Mjz94OpVtxWGvWgJmGW81HKYOJm1MEjkwi+NbGGMsakDpjwPge6RpoFE1SKlQgsZrVeDh3c0BELkL3cl3pp10jDQ/S5gNOU2X2SjhiPsHsrJl6iumO0R5gT9ItmqyS8nkJA4zE0aJnlIfhBR7/PHnFrqSiZAfqwhamOnOXfFh+PlkQjqVNKL8Ufpg0nWL/+hhSsh15lf+VcVwd9gRVqNCfrQPD7DzboFHrxr96zlSu/rMzlJdbJL2JPK9QWlafMBSNGjiUWaUskuzPM7UBW5zHOzEdpwcdS3dHPx+m4A2xwxiBnLjtfGhqsR5w+OGtNOBxCjraNz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2026 12:49:29.9029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f52b9da-06b1-4d21-e31e-08deb1b73d58 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6615 The Tegra238 PMC is largely similar to that found on earlier chips, but not completely compatible. Add support for the PMC on Tegra238. Signed-off-by: Prathamesh Shete --- drivers/soc/tegra/pmc.c | 151 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2ee6539d796a..4724b98fb1b1 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4595,6 +4595,156 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .has_single_mmio_aperture = false, }; +static const struct tegra_io_pad_soc tegra238_io_pads[] = { + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe028, 0xe02c, "hdmi-dp0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe06c, 0xe070, "ufs"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 2, 0xe040, 0xe044, "edp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe058, 0xe05c, "sdmmc1-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, "sdmmc3-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, "ao-hv"), +}; + +static const struct tegra_io_pad_vctrl tegra238_io_pad_vctrls[] = { + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0), +}; + +static const struct pinctrl_pin_desc tegra238_pin_descs[] = { + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), +}; + +static const struct tegra_pmc_regs tegra238_pmc_regs = { + .scratch0 = 0x2000, + .rst_status = 0x70, + .rst_source_shift = 0x2, + .rst_source_mask = 0xfc, + .rst_level_shift = 0x0, + .rst_level_mask = 0x3, +}; + +static const char * const tegra238_reset_sources[] = { + "SYS_RESET_N", /* 0 */ + "AOWDT", + NULL, + "BPMPWDT", + NULL, + "SPEWDT", /* 5 */ + NULL, + NULL, + "SENSOR", + NULL, + NULL, /* 10 */ + "MAINSWRST", + "SC7", + NULL, + NULL, + NULL, /* 15 */ + NULL, + NULL, + "RTC_XTAL_CSDC", + "BPMPBOOT", + "FUSECRC", /* 20 */ + NULL, + "PSCWDT", + "PSC_SW", + "CSITE_SW", + NULL, /* 25 */ + NULL, + "VREFRO_POWERBAD", + NULL, + NULL, + NULL, /* 30 */ + NULL, + NULL, + NULL, + NULL, + NULL, /* 35 */ + NULL, + NULL, + "TOP0WDT", + "TOP1WDT", + "TOP2WDT", /* 40 */ + "APE_C0WDT", + "APE_C1WDT", + "APE_C2WDT", + "APE_C3WDT", + "SCPM_SOC_XTAL", /* 45 */ + "SCPM_RTC_XTAL", + "SCPM_BPMP_CORE_CLK", + "SCPM_PSC_SE_CLK", + "FMON_32K", + "FMON_OSC", /* 50 */ + "VMON_SOC", + "VMON_CPU0", + NULL, + "POD_CPU", + "POD_GPU", /* 55 */ + "POD_RTC", + NULL, + "POD_IO", + "POD_PLUS_SOC", + "POD_PLUS_IO_VMON", /* 60 */ + "POD_PLUS_IO_PSCPLL", + "VMON_PLUS_0", + "VMON_PLUS_1", /* 63 */ +}; + +static const struct tegra_wake_event tegra238_wake_events[] = { + TEGRA_WAKE_IRQ("rtc", 73, 10), + TEGRA_WAKE_IRQ("pmu", 24, 209), + TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), + TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), + TEGRA_WAKE_IRQ("usb3-port-2", 78, 167), + TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), + TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), + TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), +}; + +static const struct tegra_pmc_soc tegra238_pmc_soc = { + .num_powergates = 0, + .powergates = NULL, + .num_cpu_powergates = 0, + .cpu_powergates = NULL, + .has_tsense_reset = false, + .has_gpu_clamps = false, + .needs_mbist_war = false, + .has_io_pad_wren = false, + .maybe_tz_only = false, + .num_io_pads = ARRAY_SIZE(tegra238_io_pads), + .io_pads = tegra238_io_pads, + .num_io_pad_vctrls = ARRAY_SIZE(tegra238_io_pad_vctrls), + .io_pad_vctrls = tegra238_io_pad_vctrls, + .num_pin_descs = ARRAY_SIZE(tegra238_pin_descs), + .pin_descs = tegra238_pin_descs, + .regs = &tegra238_pmc_regs, + .init = tegra186_pmc_init, + .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .set_wake_filters = tegra186_pmc_set_wake_filters, + .irq_set_wake = tegra186_pmc_irq_set_wake, + .irq_set_type = tegra186_pmc_irq_set_type, + .reset_sources = tegra238_reset_sources, + .num_reset_sources = ARRAY_SIZE(tegra238_reset_sources), + .reset_levels = tegra186_reset_levels, + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), + .num_wake_events = ARRAY_SIZE(tegra238_wake_events), + .wake_events = tegra238_wake_events, + .max_wake_events = 96, + .max_wake_vectors = 3, + .pmc_clks_data = NULL, + .num_pmc_clks = 0, + .has_blink_output = false, + .has_single_mmio_aperture = false, +}; + #define TEGRA264_IO_PAD_VCTRL(_id, _offset, _ena_3v3, _ena_1v8) \ ((struct tegra_io_pad_vctrl) { \ .id = (_id), \ @@ -4785,6 +4935,7 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = { static const struct of_device_id tegra_pmc_match[] = { { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, + { .compatible = "nvidia,tegra238-pmc", .data = &tegra238_pmc_soc }, { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, -- 2.25.1