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Mon, 18 May 2026 09:07:39 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Laxman Dewangan , Sowjanya Komatineni , Breno Leitao , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH 0/3] spi: tegra210-quad: Improve interrupt handling for loaded systems Date: Mon, 18 May 2026 16:07:36 +0000 Message-ID: <20260518160739.3286438-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002317:EE_|DM3PR12MB9286:EE_ X-MS-Office365-Filtering-Correlation-Id: eb8ed894-f3d4-49a6-c164-08deb4f7a83b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: dnKqvdrAeen5VVQVFrW3bKHYNQsYr1CDnouP/dzMEn5pGcbawWKDS36TG+3ZQadqilg5+blz/n4vCiNahplkMK5KOMc+km/c8U7oNeLA+E3Hxj1Quhwy61uP/Xz6qxCIEfimVWdZs9jLgULGwmgw5L8NedX/0Q5ORIcPQyeGAVKX/VYbfbPDwPuue91b6vYaGmZKB3apxV2Lu1TF+ZF7TG+HlDPlPw3mbIuY8uITwF2FN0SjaM/aWjg3+E42DCNpzsSGNOpT3VyvEF5f0MKxua4f+Vhj2oox5Zke2YL4i9Nzov5RKl+LYx74jPkITDU4JDY5o4Rfd2EvEPJjGvGdpeKYyQUM5BOhde8Af+56LB7Zqg76juK+cHTztzAhgbU1fx500nvk162RxVZesC/ffX00KS5mLMSIzHwu0hLwyEhw6ZCQ/huYCfhfIMdz4WoQkzpCZQ8H02XqOw6y6ppJOLyGp90kkdb7hv0gMmC8EqQSYOapE9lYclg+9sIsWu1U7zkdxYIH4rbpRNftQG7QIrMAZTX2I7Y3Q8KbSALmd0525bfUCUwO5AMH7Uf7xv/6ZuCBp7QRq4vNJgrLK0+CYpDQf7PizyVEL9gs1mydHJcAdV6gvO1/i3RNaN5guQtMdcm6ghuYF0gezn9otIXtJLBo6ixDIYsYBarLqq+cQBiAERs/AwoXRBh+nKyKHY2AMo1byw8qu9261+Ut0q3A120qy0psg91LfKQmtkj5vzQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(18002099003)(56012099003)(11063799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1XiUAYEQkLr+RiDIoz3bpngKdKd6YrEemViOZgYUIK8uv6UA65orJ7AhsiPt3SrK+QCT8I4h/DaSRptlseMmk30kxK29U/FwAmNs9QJ9VMS3/N1mTt6rhBqCIRCCmM9nPGE4pki1Y1xm3mf62lc2ORnNcrD1AFYt9ucP2v2o71PNuk+uI2fjwNzhPuPT0CedNO+K3Cxen0l9eeqjB4pRQH9iWaw6DtLCeFPSFiekb/gUfkBhe8F3ArifN3hIltwkWEynt9GZlC3HmzMdSgP3dWbHNliDYo4RrORzTdF9uclvdS+UjCCcvjUbcp1e6PwRfPJxX9SBZ2DxvrgJDPk7FEGhEBWYMBNaSnyzrUTMxtlgCogADQndstDyW9C8RONo2UESzI5MAKH3kowtYkyxtTARDXqtdFITC7E31WCN5c4dkYkMuXZogleQmU7Y0Ng2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 16:08:10.4237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb8ed894-f3d4-49a6-c164-08deb4f7a83b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002317.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 The current threaded IRQ implementation in spi-tegra210-quad suffers from scheduler-induced latency on heavily loaded systems. Because threaded IRQ handlers are subject to CFS scheduling, they can be delayed long enough to trigger transfer timeouts even though hardware completes in microseconds. This results in false timeout errors and WARN_ON splats during normal operation. This series addresses the problem in three steps: 1. Convert the threaded IRQ handler to a hard IRQ + high-priority unbound workqueue model. The hard IRQ does the minimum: verify interrupt ownership, cache status registers, clear and mask interrupts. The workqueue bottom-half handles the rest in process context and can run on any available CPU, avoiding the CPU0 bottleneck inherent in threaded IRQs. 2. Cache QSPI_TRANS_STATUS in the ISR before clearing it. This allows the timeout handler to distinguish between a real hardware timeout (QSPI_RDY not set) and a delayed workqueue (QSPI_RDY set), preventing false timeout errors when hardware has already completed. 3. Process small PIO transfers (≤ FIFO depth, 256 bytes) directly in hard IRQ context. This eliminates workqueue scheduling overhead for latency-sensitive devices like TPMs, reducing completion latency from potentially seconds to microseconds. Tested on TH500 with TPM and QSPI flash devices under sustained load. The series applies cleanly on top of linux-next (20260508). Vishwaroop A (3): spi: tegra210-quad: Convert to hard IRQ with high-priority workqueue spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler spi: tegra210-quad: Process small PIO transfers in hard IRQ context drivers/spi/spi-tegra210-quad.c | 169 ++++++++++++++++++++++---------- 1 file changed, 117 insertions(+), 52 deletions(-) -- 2.17.1