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Mon, 18 May 2026 09:07:40 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Laxman Dewangan , Sowjanya Komatineni , Breno Leitao , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH 2/3] spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler Date: Mon, 18 May 2026 16:07:38 +0000 Message-ID: <20260518160739.3286438-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260518160739.3286438-1-va@nvidia.com> References: <20260518160739.3286438-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002317:EE_|BN3PR12MB9571:EE_ X-MS-Office365-Filtering-Correlation-Id: 662bdc37-3042-4ea7-a920-08deb4f7a8df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|11063799003|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zf04ilzK+2L/PEb+ucaO/ijxEkBaU4yfeOxcOnMoEeO5E2gfnQUNNAxCPrQpW5R5eI14lI1xmFCh4blnO+T9xG+dG8R1xQZKnZwldXVucjBlVD1OHWzULVTQF8++DdJijT0MNSi5oc8N2O5L6aYaYmn59FU9YTMxejL77O61J9YkDIex34MkhP/6ADUSpmaUZCoZcx+I7cCMQEsX8tuBEbpEPbrygz5zyQN43Fm5s6yMIbqgHgkuBXlEUoe8EZkicYGR7yYk5CW0L3lDAastFnPQcjYn1BIHTHkWqP3uWOoCtLMjZcy1KS/xMNdjfgxeHiCdBg4T7ebpjlh28hJkeCfyR3vTU0EDZPeEQVZRDFwdfwm3KsdEbB9yjQr/e16a7yfvciuSvaTAy2QuCVgTKYaYD5F4fe977KFzlNm6SXorL6wMdXLCnSpjoGi4NV5a X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 16:08:11.4918 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 662bdc37-3042-4ea7-a920-08deb4f7a8df X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002317.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR12MB9571 On heavily loaded systems, workqueue scheduling delays can exceed the transfer timeout even though hardware completes the transfer in microseconds. The timeout handler cannot distinguish between a real hardware timeout and a delayed workqueue, causing false timeout errors. Cache QSPI_TRANS_STATUS in the ISR before clearing it, allowing the timeout handler to check if hardware completed (QSPI_RDY set) versus a real timeout (QSPI_RDY not set). This prevents false timeout errors when the hardware completes but the workqueue is delayed. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 42 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index a551c7a7f6c4..6148267a51cd 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -214,6 +214,7 @@ struct tegra_qspi { u32 tx_status; u32 rx_status; u32 status_reg; + u32 trans_status; bool is_packed; bool use_dma; @@ -854,6 +855,7 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran tqspi->cur_rx_pos = 0; tqspi->cur_tx_pos = 0; tqspi->curr_xfer = t; + tqspi->trans_status = 0; spin_unlock_irqrestore(&tqspi->lock, flags); if (is_first_of_msg) { @@ -1068,26 +1070,32 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi); */ static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) { + unsigned long flags; irqreturn_t ret; - u32 status; + u32 trans_status; - /* Check if hardware actually completed the transfer */ - status = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - if (!(status & QSPI_RDY)) + spin_lock_irqsave(&tqspi->lock, flags); + + trans_status = tqspi->trans_status; + if (!(trans_status & QSPI_RDY)) { + spin_unlock_irqrestore(&tqspi->lock, flags); return -ETIMEDOUT; + } /* - * Hardware completed but interrupt was lost/delayed. Manually - * process the completion by calling the appropriate handler. + * ISR or workqueue may have already completed the transfer + * and NULLed curr_xfer between the completion timeout and now. */ + if (!tqspi->curr_xfer) { + spin_unlock_irqrestore(&tqspi->lock, flags); + return 0; + } + + spin_unlock_irqrestore(&tqspi->lock, flags); + dev_warn_ratelimited(tqspi->dev, "QSPI interrupt timeout, but transfer complete\n"); - /* Clear the transfer status */ - status = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); - tegra_qspi_writel(tqspi, status, QSPI_TRANS_STATUS); - - /* Manually trigger completion handler */ if (!tqspi->is_curr_dma_xfer) ret = handle_cpu_based_xfer(tqspi); else @@ -1227,9 +1235,9 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, if (ret == 0) { /* - * Check if hardware completed the transfer - * even though interrupt was lost or delayed. - * If so, process the completion and continue. + * Check if hardware completed the transfer even though + * workqueue was delayed. If so, process completion and + * continue. */ ret = tegra_qspi_handle_timeout(tqspi); if (ret < 0) { @@ -1346,8 +1354,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, if (ret == 0) { /* * Check if hardware completed the transfer even though - * interrupt was lost or delayed. If so, process the - * completion and continue. + * workqueue was delayed. If so, process completion and + * continue. */ ret = tegra_qspi_handle_timeout(tqspi); if (ret < 0) { @@ -1642,6 +1650,8 @@ static irqreturn_t tegra_qspi_isr(int irq, void *context_data) if (!(status & QSPI_RDY)) return IRQ_NONE; + tqspi->trans_status = status; + spin_lock(&tqspi->lock); tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); tegra_qspi_mask_clear_irq(tqspi); -- 2.17.1