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Mon, 18 May 2026 09:07:41 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Laxman Dewangan , Sowjanya Komatineni , Breno Leitao , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH 3/3] spi: tegra210-quad: Process small PIO transfers in hard IRQ context Date: Mon, 18 May 2026 16:07:39 +0000 Message-ID: <20260518160739.3286438-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260518160739.3286438-1-va@nvidia.com> References: <20260518160739.3286438-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4D:EE_|CH1PPF68E8581EB:EE_ X-MS-Office365-Filtering-Correlation-Id: 06c335de-f178-4519-70ce-08deb4f7a6f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|11063799003|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YvokVPqweF+7+cr23Bina2vThS32auPD0uufZUqp9xReHIPkiWYSuIwG8JB2cgxBBGxxnu7QIMBvPl2rPUWgwctfpsPMwGKFh7Od4Ih6hMe/nzNMnoAxTrcqpznKKyDC0j4SiRaklipUpqucyNH7o7h8v4c3umgKVRew/zAEkbLoEpAGHeK4mQ7Kbjhj8N4ILvhaY8HN13fHFpx9lgMTexIraI0++mL4+gA4YI0xoLxjCqeail5V6JhIdMnHLJd3Ol45jtOXznYgc9OuntjqG7vDLFjiSV+lTMmCmvgTM0vdgPni5nyK6SHO9iZOh8ZPNgxgY80K55HmPsAp1LqHa0rQMrKXfuMAJuPlCmpA7d4vbDUs93F3m2IVkK92XdZ6n2+ywIiA9Cl3NJzBDXUBpIcQstmSikuV4q0JOEx4FvWtMo4SrGxFwIVzCNGtxI+C X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2026 16:08:08.2550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06c335de-f178-4519-70ce-08deb4f7a6f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF68E8581EB On heavily loaded systems, workqueue scheduling delays can exceed transfer timeouts even for high-priority queues, causing false timeouts for latency-sensitive devices like TPM despite hardware completing in microseconds. Process small PIO transfers (≤256 bytes) directly in hard IRQ context instead of deferring to workqueue. This reduces completion latency from 1000ms+ to microseconds and matches the pattern used by other SPI drivers. The 256-byte threshold (FIFO depth) ensures small transfers for devices like TPMs use the fast path, while larger transfers continue using workqueue. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 6148267a51cd..435e14d80bfa 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1666,6 +1666,15 @@ static irqreturn_t tegra_qspi_isr(int irq, void *context_data) spin_unlock(&tqspi->lock); + /* + * For small PIO transfers (e.g., TPM), process directly in hard IRQ + * context unless there was a FIFO error. Error recovery calls + * device_reset() which can sleep, so must be deferred to workqueue. + */ + if (!tqspi->is_curr_dma_xfer && tqspi->curr_dma_words <= QSPI_FIFO_DEPTH && + !tqspi->tx_status && !tqspi->rx_status) + return handle_cpu_based_xfer(tqspi); + queue_work(tqspi->wq, &tqspi->irq_work); return IRQ_HANDLED; -- 2.17.1