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Wed, 20 May 2026 12:24:07 -0700 From: Vishwaroop A To: Thierry Reding , Jonathan Hunter , Mark Brown CC: Vishwaroop A , Breno Leitao , "Laxman Dewangan" , Sowjanya Komatineni , Suresh Mangipudi , "Krishna Yarlagadda" , , , Subject: [PATCH v3 3/3] spi: tegra210-quad: Process small PIO transfers in hard IRQ context Date: Wed, 20 May 2026 19:24:05 +0000 Message-ID: <20260520192405.70469-4-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260520192405.70469-1-va@nvidia.com> References: <20260520192405.70469-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|CH3PR12MB7665:EE_ X-MS-Office365-Filtering-Correlation-Id: 635036b9-abd9-4f02-b6b4-08deb6a568af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|11063799006|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: W5wLqT+iMmqHXK6CaNT6PUXauOuok32uUxARUo1SMPeQCsfnw1nYljgTLz/AppGJiDxR1k5XxOykrqg7+4sLG+RsT8RAXxC8tE8LvZyIWHl7+KSekz5V+6Pu65ZaRy0MGmN1+1qdiVc5tvlFUd2H9w+lE1H+gL2RqdnlbxZDVpX9R36DvOWamWcRCNw1FJ3E6aZkN4+mMK2Mtkq2f4BcupxkEAyoI5tNJxYWv6HRjL0rnAmBofSLD/FL+CXvr2kWrOYNGNcqd9AR0RUIAheDxLKdjNuU95J7M5t4TR7dfZ7IcQTPli+1pU/Q+lkjR50YyBtQFpKRjW3+lAgTYeGSTPAwIkSnPujwnVB4udeTKknxd/9eLEgughECtiFf1ly2YwAmPr1hwR/Q0kaKVZd+/6EShx6glRXpocH50KLWoz7Z62OzHwoQ5r7WGjVrmHsD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 19:24:27.4106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 635036b9-abd9-4f02-b6b4-08deb6a568af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7665 On heavily loaded systems, workqueue scheduling delays can exceed transfer timeouts even for high-priority queues, causing false timeouts for latency-sensitive devices like TPM despite hardware completing in microseconds. Process small PIO transfers (≤256 bytes) directly in hard IRQ context instead of deferring to workqueue. This reduces completion latency from 1000ms+ to microseconds and matches the pattern used by other SPI drivers. The 256-byte threshold (FIFO depth) ensures small transfers for devices like TPMs use the fast path, while larger transfers continue using workqueue. Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 64ad17d38b84..e3681f06b0ec 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1664,6 +1664,15 @@ static irqreturn_t tegra_qspi_isr(int irq, void *context_data) spin_unlock(&tqspi->lock); + /* + * For small PIO transfers (e.g., TPM), process directly in hard IRQ + * context unless there was a FIFO error. Error recovery calls + * device_reset() which can sleep, so must be deferred to workqueue. + */ + if (!tqspi->is_curr_dma_xfer && tqspi->curr_dma_words <= QSPI_FIFO_DEPTH && + !tqspi->tx_status && !tqspi->rx_status) + return handle_cpu_based_xfer(tqspi); + queue_work(tqspi->wq, &tqspi->irq_work); return IRQ_HANDLED; -- 2.17.1