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Thu, 28 May 2026 03:16:28 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum Date: Thu, 28 May 2026 10:16:16 +0000 Message-ID: <20260528101617.4068249-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260528101617.4068249-1-amhetre@nvidia.com> References: <20260528101617.4068249-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD79:EE_|MN0PR12MB5738:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c7a0cc4-d2d6-480f-5757-08debca2366c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|56012099006|11063799006|3023799007|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qPg3d4pq/VEy5XksHMNzfTWne8GgywLp7B7lrPB2g9UaUY8ga0jfY5tuZigssJz2vWJaYUp5evBT0F5G9Xn6vgX15xa6oERry0DerhtYaqttrWDplFSx6Oye2Xjs80giEVY6teTDsf2DUBhALEzfSwlnwWkyLbmz2iVY1W6T5oC18cOmAAAoxb6zsI7x0QWUTXKd3LsZs76DJtEJttd3GY1F6OImYjX5cxa8M5/gNUhgNBMNUhaERCq6eudpR2nSwNe2zAtIF4BP+1W628/3lVJAKBSWJj3sXpLbSd3P4JuBywBuSfuXk7d202t7LCU0VjYiqamhbP65aVYG8rVK6jUaFElGc77AXIgo5ktBIpfcZKEweD4pTUatZOTFU8XMUpik3InD/NqIc1PoyuYpqzCRn1stNrBG0Lo1N/xGu7nMVLu//jjUmRMddmcs+vN8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 10:16:41.5404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c7a0cc4-d2d6-480f-5757-08debca2366c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD79.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5738 Tegra264 SMMU is affected by erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. No callers consume the option yet, next patch wires the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 +++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 9be589d14a3b..88296c0a5337 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -5229,8 +5229,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |= ARM_SMMU_OPT_TLBI_TWICE; + } return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 16353596e08a..08d1abaf31ae 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -928,6 +928,14 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Tegra264 erratum: a TLB entry can survive an invalidation that races + * with concurrent traffic targeting the same entry. The software + * workaround is to issue every CFGI/TLBI command twice, each followed + * by CMD_SYNC. The second issue is guaranteed to evict the entry. + * ATC_INV commands are not affected and must not be doubled. + */ +#define ARM_SMMU_OPT_TLBI_TWICE (1 << 5) u32 options; struct arm_smmu_cmdq cmdq; -- 2.50.1