From: Ashish Mhetre <amhetre@nvidia.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <joro@8bytes.org>,
<jgg@ziepe.ca>, <nicolinc@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Ashish Mhetre <amhetre@nvidia.com>
Subject: [PATCH v2 0/2] iommu/arm-smmu-v3: Tegra264 invalidation workaround
Date: Fri, 29 May 2026 14:08:28 +0000 [thread overview]
Message-ID: <20260529140830.629738-1-amhetre@nvidia.com> (raw)
Nvidia Tegra264 SMMUs are affected by an erratum where a TLB entry can
survive an invalidation that races with concurrent traffic targeting
the same entry. The hardware-recommended software workaround is to
issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The
second issue must execute only after the first issue's CMD_SYNC has
completed, giving the sequence:
TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC
ATC_INV is not affected and must not be doubled.
This series implements the workaround by hooking the duplication into
the single chokepoint that every synchronous submission flows through,
arm_smmu_cmdq_issue_cmdlist().
Patch 1 detects affected instances using the existing
"nvidia,tegra264-smmu" compatible string and exposes the condition
via a new ARM_SMMU_OPT_TLBI_TWICE option bit.
Patch 2 wires the option into the CMDQ submission path: when @sync is
true and the cmdlist carries a CFGI/TLBI opcode, the same cmdlist is
re-issued a second time. The batch capacity-rollover path is also
adjusted to force a SYNC on chunks that carry CFGI/TLBI commands so
each flushed chunk is correctly doubled.
The series is based on Jason Gunthorpe's "Remove SMMUv3
struct arm_smmu_cmdq_ent" series [1], specifically commit 13428b0bf794
("iommu/arm-smmu-v3: Directly encode TLBI commands") which is the
final patch of that series in linux-next.
[1] https://lore.kernel.org/all/177919957385.1012282.14787407041669291032.b4-ty@kernel.org/
Changes since v1:
- Patch 1: Add IIDR/IDR/ACPI rationale to the commit message, explaining
why the erratum is detected from the device tree compatible string
rather than from a HW register or ACPI/IORT.
- Rebased onto the publicly accessible base 13428b0bf794 (final commit
of Jason's series in linux-next) so that the base-commit is resolvable
on lore.kernel.org.
- Patch 2: Picked up Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>.
- No code changes since v1.
Ashish Mhetre (2):
iommu/arm-smmu-v3: Detect Tegra264 erratum
iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 70 +++++++++++++++++++--
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 +++
2 files changed, 72 insertions(+), 6 deletions(-)
base-commit: 13428b0bf7947098daf9a1db14a74d33eb1b5079
--
2.50.1
next reply other threads:[~2026-05-29 14:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 14:08 Ashish Mhetre [this message]
2026-05-29 14:08 ` [PATCH v2 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum Ashish Mhetre
2026-05-29 21:30 ` Nicolin Chen
2026-06-01 9:04 ` Ashish Mhetre
2026-05-29 14:08 ` [PATCH v2 2/2] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Ashish Mhetre
2026-05-29 21:10 ` Nicolin Chen
2026-06-01 9:20 ` Ashish Mhetre
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