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Tue, 9 Jun 2026 00:32:07 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v4 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Date: Tue, 9 Jun 2026 07:32:02 +0000 Message-ID: <20260609073204.1760077-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260609073204.1760077-1-amhetre@nvidia.com> References: <20260609073204.1760077-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|PH0PR12MB7816:EE_ X-MS-Office365-Filtering-Correlation-Id: 40360114-49cb-4c6e-6334-08dec5f940f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|18002099003|22082099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8+Eu2dZ//Jz3OHYYzLYbdt0ADHDhoAUqX2LBC/4OLAYE3M7Ly3aNreX/02DHSYiFLXl65CekPj22y4d2yfkoasHPgMZ9a9DTjGXzIl+5Ovm62FxHM5rvSUBUUlvqQBjeUWnFDgh6QNuI8Ia/nTSWuZ9WEwsG5wh8BwRrxGz3PP82sU+V+xOZcjUJwoSm+WH4V90l4nJ+hEeRTeNT0WqOvAu+dHPZ+rtBxvwd5tfhevrRthW6qW5luiQj62XbR78CrdfF4AIsSP8XhlV4maZGkU2159AsfuCl8jWvNZpe/muoqq23W5B97AnnFxC6slLJzlnHFL/jYpZtApNeP7KJUXXBer0HhiFqdWYvWibC+sDM9DMX9VAmEQUNEcM5G5BQJvBTYsNBhdTiuNTu1gf/GmuqW/beLWYJTYwIaIvf9XYaYklAmdH7j9FdWT5V4/qS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 07:32:25.9798 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40360114-49cb-4c6e-6334-08dec5f940f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7816 From: Nicolin Chen arm_smmu_cmdq_batch_add_cmd_p() carries two distinct reasons for flushing the current batch with a CMD_SYNC before appending the new command: - The batch's pre-assigned cmdq does not support the new command. - The Arm erratum 2812531 workaround (ARM_SMMU_OPT_CMDQ_FORCE_SYNC) forces a SYNC at one entry before the batch is full. Lift those checks into a new arm_smmu_cmdq_batch_force_sync() helper so that adding another force-sync condition becomes a one-line addition. No functional change. Signed-off-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 +++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a10affb483a4..76efe479e80f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -847,16 +847,27 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu, cmds->cmdq = arm_smmu_get_cmdq(smmu, cmd); } +static bool arm_smmu_cmdq_batch_force_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmd *cmd) +{ + /* The batch's pre-assigned cmdq doesn't support the new command */ + if (!arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) + return true; + + /* Arm erratum 2812531 */ + if (cmds->num == CMDQ_BATCH_ENTRIES - 1 && + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return true; + + return false; +} + static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds, struct arm_smmu_cmd *cmd) { - bool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) && - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); - bool unsupported_cmd; - - unsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); - if (force_sync || unsupported_cmd) { + if (arm_smmu_cmdq_batch_force_sync(smmu, cmds, cmd)) { arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, cmds->num, true); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); -- 2.50.1