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Tue, 9 Jun 2026 00:32:08 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v4 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Date: Tue, 9 Jun 2026 07:32:03 +0000 Message-ID: <20260609073204.1760077-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260609073204.1760077-1-amhetre@nvidia.com> References: <20260609073204.1760077-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E62:EE_|SA1PR12MB6896:EE_ X-MS-Office365-Filtering-Correlation-Id: 93fa9eed-09dd-49d8-9ddd-08dec5f940ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|6133799003|18002099003|22082099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: T5ZH+cSho6hqwHcHAGw9TUGyEsXs73J+XnQb9iPj/J8145pi+fbUoigcQDxnO/AwPNwjQGe/waOXv095R2gHTZ6Eh3mHAqgTPmrPnVqAFRtjgSYKk6IQ/G5Gnl1aC12vFgFMx3fGKjO/HF8fF4wKG9ubNhGl4z3+Sj0ukEcws5cjDJrbWNFaojwH2oyBIfkkWR0znGxre9k8XD5aZ62EUqH+PpsNnJsKxDppXyUlajbKpU9qnhmb42Fxwj3F6sWDRclr5xu0qqY+3S+37vHTXfErLfIHk2mgO6JOW4B2WBK9h6pSdg6FePt4bAb5TJpXC65IQdX5DGUS9P02lRuyzv8rtKca2JMNzV7w1nlIsW1Hpio5nADvbQNe46Wetma7sJD+RUL6L3sycvRZa84acB1utWuLrv4ie5DSwbUh3LJwcGmayF/buf3PPQ4eG9Wu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 07:32:25.4992 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93fa9eed-09dd-49d8-9ddd-08dec5f940ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E62.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6896 Tegra264 SMMU is affected by an erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware registers. Tegra264 boots from device tree only and has no ACPI/IORT support, so detection is through device tree only. Add the ARM_SMMU_OPT_REPEAT_TLBI_CFGI option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. Also add a matching arm_smmu_erratum_repeat_tlbi_cfgi_key static key that DT probe enables, so the inline classifier compiles down to a single test+branch on unaffected kernels. Add an arm_smmu_erratum_cmd_needs_repeating() helper in arm-smmu-v3.h that gates on the static key first and then range-checks the opcode (CFGI_STE .. ATC_INV), so subsequent changes wiring the workaround into the CMDQ submission and iommufd batching paths can share a single predicate. No callers consume the option yet. A subsequent change wires the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 24 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 76efe479e80f..599c835c50d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -42,6 +42,8 @@ MODULE_PARM_DESC(disable_msipolling, static const struct iommu_ops arm_smmu_ops; static struct iommu_dirty_ops arm_smmu_dirty_ops; +DEFINE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); + enum arm_smmu_msi_index { EVTQ_MSI_INDEX, GERROR_MSI_INDEX, @@ -5303,8 +5305,11 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |= ARM_SMMU_OPT_REPEAT_TLBI_CFGI; + static_branch_enable(&arm_smmu_erratum_repeat_tlbi_cfgi_key); + } return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index c909c9a88538..c6ea3b8dc761 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -928,6 +929,12 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Repeat every {CFGI,TLBI};CMD_SYNC command sequence so that the second + * issue executes only after the first issue's CMD_SYNC has completed. + * Does not apply to ATC_INV. + */ +#define ARM_SMMU_OPT_REPEAT_TLBI_CFGI (1 << 5) u32 options; struct arm_smmu_cmdq cmdq; @@ -1212,6 +1219,23 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmds, int n, bool sync); +DECLARE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); + +static inline bool +arm_smmu_erratum_cmd_needs_repeating(struct arm_smmu_device *smmu, + struct arm_smmu_cmd *cmd) +{ + u8 opcode; + + if (!static_branch_unlikely(&arm_smmu_erratum_repeat_tlbi_cfgi_key)) + return false; + if (!(smmu->options & ARM_SMMU_OPT_REPEAT_TLBI_CFGI)) + return false; + + opcode = FIELD_GET(CMDQ_0_OP, cmd->data[0]); + return opcode >= CMDQ_OP_CFGI_STE && opcode < CMDQ_OP_ATC_INV; +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); void arm_smmu_sva_notifier_synchronize(void); -- 2.50.1