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Wed, 24 Jun 2026 03:23:56 -0700 From: Akhil R To: Alexandre Belloni CC: Frank Li , Miquel Raynal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guenter Roeck , Philipp Zabel , Jon Hunter , Thierry Reding , , , , , , Akhil R Subject: [PATCH v5 08/12] i3c: dw-i3c-master: Add ACPI core clock frequency quirk Date: Wed, 24 Jun 2026 10:21:02 +0000 Message-ID: <20260624102153.1770072-9-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260624102153.1770072-1-akhilrajeev@nvidia.com> References: <20260624102153.1770072-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|DS7PR12MB8417:EE_ X-MS-Office365-Filtering-Correlation-Id: 800cbe4f-7942-465c-73d1-08ded1dac13a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|376014|36860700016|7416014|1800799024|3023799007|56012099006|11063799006|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7KCGYwmiOHyhLewYq7fNCwcn4/nyAp+u6WezNYQWNNa/3uwcoIWc+OMe0+IuRyGKLqC9uXP3itOp/EKgdt8mjAIsZsokGwmj5UF72Pa6vtiTyP9gpqxHStSzRAuzbqMiRYdhgp6TjUtVQ9Y6KAFguJigEGcOsiskkPgyNPw8cKbNarbwqMcSAvdopOmQUuy18OU0bjuaHWLfCP+OCWWwsCOtTLCfS3IzR+PO24ih3jdcCL1Fa2TkzjbOd+NfDiQO71TF6ykN3HykNkLykf5Ur1hsV/r80PAXXTrwZAnT/+1zFzRa4A0M7glIuhuPsPwFFk5AZvMc+SQ2gV753BbCarQbvic05JJJZ6D06prXvS35SatqouFVtrmcd1K6e1SRMXMWpVCSFOarCOOpTeLmgo7Xuua5mZHh0Hg7ScUwtH67xcwI7egqbPYfXkSWr0sp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2026 10:24:20.6603 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 800cbe4f-7942-465c-73d1-08ded1dac13a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8417 Some ACPI-enumerated devices like Tegra410 do not expose the controller core clock through the clk framework. Unlike device tree, ACPI on Arm does not model clock providers. The hardware is expected to have its clocks enabled by firmware before the OS takes over. Make the core clock optional and allow selected ACPI devices to provide the core clock rate through the "clock-frequency" _DSD property when the core clock is absent. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c index 29030fd9594a..8e40d178d500 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -242,6 +242,7 @@ /* List of quirks */ #define AMD_I3C_OD_PP_TIMING BIT(1) #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) +#define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) struct dw_i3c_cmd { u32 cmd_lo; @@ -556,13 +557,33 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); } +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *master) +{ + unsigned int core_rate_prop; + + if (master->core_clk) + return clk_get_rate(master->core_clk); + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) { + dev_err(master->dev, "missing core clock\n"); + return 0; + } + + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_prop)) { + dev_err(master->dev, "missing clock-frequency property\n"); + return 0; + } + + return core_rate_prop; +} + static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { unsigned long core_rate, core_period; u32 scl_timing; u8 hcnt, lcnt; - core_rate = clk_get_rate(master->core_clk); + core_rate = dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; @@ -615,7 +636,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master) u16 hcnt, lcnt; u32 scl_timing; - core_rate = clk_get_rate(master->core_clk); + core_rate = dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; @@ -1577,7 +1598,7 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, if (IS_ERR(master->regs)) return PTR_ERR(master->regs); - master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL); + master->core_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); if (IS_ERR(master->core_clk)) return PTR_ERR(master->core_clk); -- 2.43.0