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This keeps validation of base, size, interleave, target type, and enable state in one place before adding another HDM parser. Signed-off-by: Srirangan Madhavan --- drivers/cxl/core/hdm.c | 61 +++++++++++----------------------------- drivers/cxl/core/reset.c | 45 +++++++++++++++++++++++++++++ include/cxl/cxl.h | 3 ++ 3 files changed, 64 insertions(+), 45 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 83cda63f76a5..e9e00c68a0ad 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -952,6 +952,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, u32 remainder; int i, rc; u32 ctrl; + struct cxl_decoder_settings settings; union { u64 value; unsigned char target_id[8]; @@ -968,35 +969,28 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, lo = readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(which)); hi = readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(which)); size = (hi << 32) + lo; - committed = !!(ctrl & CXL_HDM_DECODER0_CTRL_COMMITTED); + lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which)); + hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which)); + target_list.value = (hi << 32) + lo; + rc = cxl_hdm_decode_decoder(&settings, which, ctrl, base, size, + target_list.value, &committed); + if (rc) { + dev_warn(&port->dev, + "decoder%d.%d: Invalid decoder configuration (ctrl: %#x): %d\n", + port->id, cxld->id, ctrl, rc); + return rc; + } + cxld->commit = cxl_decoder_commit; cxld->reset = cxl_decoder_reset; - - if (!committed) - size = 0; - if (base == U64_MAX || size == U64_MAX) { - dev_warn(&port->dev, "decoder%d.%d: Invalid resource range\n", - port->id, cxld->id); - return -ENXIO; - } + cxld->settings = settings; + size = range_len(&cxld->hpa_range); if (info) cxled = to_cxl_endpoint_decoder(&cxld->dev); - cxld->hpa_range = (struct range) { - .start = base, - .end = base + size - 1, - }; /* decoders are enabled if committed */ if (committed) { - cxld->flags |= CXL_DECODER_F_ENABLE; - if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) - cxld->flags |= CXL_DECODER_F_LOCK; - if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl)) - cxld->target_type = CXL_DECODER_HOSTONLYMEM; - else - cxld->target_type = CXL_DECODER_DEVMEM; - guard(rwsem_write)(&cxl_rwsem.region); if (cxld->id != cxl_num_decoders_committed(port)) { dev_warn(&port->dev, @@ -1036,32 +1030,11 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which)); } } - rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl), - &cxld->interleave_ways); - if (rc) { - dev_warn(&port->dev, - "decoder%d.%d: Invalid interleave ways (ctrl: %#x)\n", - port->id, cxld->id, ctrl); - return rc; - } - rc = eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl), - &cxld->interleave_granularity); - if (rc) { - dev_warn(&port->dev, - "decoder%d.%d: Invalid interleave granularity (ctrl: %#x)\n", - port->id, cxld->id, ctrl); - return rc; - } - dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n", port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end, cxld->interleave_ways, cxld->interleave_granularity); if (!cxled) { - lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which)); - hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which)); - target_list.value = (hi << 32) + lo; - cxld->targets = target_list.value; for (i = 0; i < cxld->interleave_ways; i++) cxld->target_map[i] = target_list.target_id[i]; @@ -1078,9 +1051,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, port->id, cxld->id, size, cxld->interleave_ways); return -ENXIO; } - lo = readl(hdm + CXL_HDM_DECODER0_SKIP_LOW(which)); - hi = readl(hdm + CXL_HDM_DECODER0_SKIP_HIGH(which)); - skip = (hi << 32) + lo; + skip = cxld->skip; rc = devm_cxl_dpa_reserve(cxled, *dpa_base + skip, dpa_size, skip); if (rc) { dev_err(&port->dev, diff --git a/drivers/cxl/core/reset.c b/drivers/cxl/core/reset.c index 14f024098e82..4c977fc47f8d 100644 --- a/drivers/cxl/core/reset.c +++ b/drivers/cxl/core/reset.c @@ -116,3 +116,48 @@ int cxl_commit(struct cxl_decoder_settings *settings, void __iomem *hdm) return 0; } EXPORT_SYMBOL_FOR_MODULES(cxl_commit, "cxl_core"); + +int cxl_hdm_decode_decoder(struct cxl_decoder_settings *settings, int id, + u32 ctrl, u64 base, u64 size, u64 target_or_skip, + bool *committed) +{ + bool enabled = FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl); + int rc; + + *settings = (struct cxl_decoder_settings) { + .id = id, + .targets = target_or_skip, + .target_type = FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) ? + CXL_DECODER_HOSTONLYMEM : CXL_DECODER_DEVMEM, + }; + + if (committed) + *committed = enabled; + if (!enabled) + size = 0; + if (base == U64_MAX || size == U64_MAX || + (size && base > U64_MAX - (size - 1))) + return -ENXIO; + if (enabled && !size) + return -ENXIO; + + settings->hpa_range = (struct range) { + .start = base, + .end = base + size - 1, + }; + if (enabled) { + settings->flags = CXL_DECODER_F_ENABLE; + if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK) + settings->flags |= CXL_DECODER_F_LOCK; + } + + rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl), + &settings->interleave_ways); + if (rc) + return rc; + + return eig_to_granularity(FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, + ctrl), + &settings->interleave_granularity); +} +EXPORT_SYMBOL_FOR_MODULES(cxl_hdm_decode_decoder, "cxl_core"); diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 84924ca06e52..80839517eabf 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -133,6 +133,9 @@ struct cxl_hdm_info { struct cxl_decoder_settings settings[] __counted_by(decoder_count); }; +int cxl_hdm_decode_decoder(struct cxl_decoder_settings *settings, int id, + u32 ctrl, u64 base, u64 size, u64 target_or_skip, + bool *committed); int cxl_commit(struct cxl_decoder_settings *settings, void __iomem *hdm); struct cxl_reg_map { -- 2.43.0