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Thu, 9 Jul 2026 02:56:20 -0700 From: Ashish Mhetre To: CC: , Ashish Mhetre Subject: [PATCH v5 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Date: Thu, 9 Jul 2026 09:56:10 +0000 Message-ID: <20260709095613.831769-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260709095613.831769-1-amhetre@nvidia.com> References: <20260709095613.831769-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F0:EE_|PH7PR12MB5976:EE_ X-MS-Office365-Filtering-Correlation-Id: 80adb1df-1cd0-4b3f-953a-08dedda06169 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|23010399003|11063799006|6133799003|56012099006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: O3QAjo78HmDRt6m7rv+Ol6itTtdGt2r4DXbZ++O20DwykvhpQLkYMRfWZwDFQH0PWd1YbF/C3Q/bUVA+C5Unc09gGr/Mv9K13q9pWAKDokgBLbK8/hvYP5i384S889hLozqmnrXmjrpH+Y1Ac6Pj5Yph0Ss+0iSNhc7Ca0S5xwlhbYxixXE08c7KRa+SLS6Yu8pb1ZUFGNOCWQCqqHONmUp/OpMPXclHJQ7e8visM4I9v4eA06nMglSHIBos1KP7nM6wo4KdLhliYztwpWR7kry2ERPj3tBnLpYoEPp+4rWJ3rFiCd25rpgpWSCAhuVG0xk7O9THU/36or1MdCMJFm29EhaieYqSbgqzxES0U+dFp8ZIwLY0X5TZB5CMWjRshJkMb/CeLg3lJx2gvHjdoNY3bLrAibQmQNCHeBVo+JyR+TkUyoiKUA92hJL266sp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 09:56:42.7850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80adb1df-1cd0-4b3f-953a-08dedda06169 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5976 Nvidia Tegra264 SMMUs are affected by an erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue must execute only after the first issue's CMD_SYNC has completed, giving the sequence: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware ID. Tegra264 is device-tree-only (no ACPI/IORT support), so detection is purely by compatible string. This series is structured as a small refactor + infrastructure + enable sequence so that each step is reviewable in isolation: 1/3 Pure refactor (no functional change): lift the existing force-sync conditions out of arm_smmu_cmdq_batch_add_cmd_p() into a new arm_smmu_cmdq_batch_force_sync() helper, so that adding another condition (in patch 2) is a one-line addition. Authored by Nicolin Chen. 2/3 Add the workaround infrastructure without enabling it. Defines the arm_smmu_erratum_repeat_tlbi_cfgi_key static key, the shared arm_smmu_erratum_cmd_needs_repeating() predicate, the arm_smmu_cmdq_issue_cmdlist() wrapper that can re-issue matching cmdlists, the batch-helper force-sync condition, and the iommufd batching split for mixed command classes. 3/3 Enable the workaround for the existing "nvidia,tegra264-smmu" compatible and document the erratum in silicon-errata.rst. The series applies cleanly on linux-next/master (base-commit below). Changes since v4: - Drop ARM_SMMU_OPT_REPEAT_TLBI_CFGI entirely: the option bit was set and read on the exact same "nvidia,tegra264-smmu" compatible as the static key, so it added no per-instance signal that the static key did not already carry. The predicate now gates purely on arm_smmu_erratum_repeat_tlbi_cfgi_key. (Nicolin: "Are they redundant? / Drop the deadcode then.") - Reorder the series so the compatible-string detection lands last, once all the infrastructure exists (Nicolin): 1/3 factor out force_sync helper (unchanged) 2/3 add static key + WAR functions (no functional change) 3/3 enable the key on nvidia,tegra264-smmu + silicon-errata Split the old v4 "Detect" and "Issue twice" patches accordingly. - Update the /* See ARM_SMMU_OPT_REPEAT_TLBI_CFGI */ comment inside arm_smmu_cmdq_batch_force_sync() to reference arm_smmu_erratum_cmd_needs_repeating() instead. Changes since v3: - Drop the cmds->num == 0 early-return so the refactor is truly "no functional change". - Rename ARM_SMMU_OPT_TLBI_TWICE -> ARM_SMMU_OPT_REPEAT_TLBI_CFGI and rephrase its kdoc to be hardware-agnostic. - Rename arm_smmu_cmd_needs_tlbi_twice() -> arm_smmu_erratum_cmd_needs_repeating() and drop the kdoc above it. - Replace the explicit opcode switch with a single range check opcode >= CMDQ_OP_CFGI_STE && opcode < CMDQ_OP_ATC_INV. - Introduce arm_smmu_erratum_repeat_tlbi_cfgi_key static key: the predicate gates on it first so unaffected kernels pay only a single static_branch_unlikely() check. - Drop the verbose Tegra264-specific comments above arm_vsmmu_can_batch_cmd() and inside the batch helper. - Document the erratum in Documentation/arch/arm64/silicon-errata.rst. - Guard the repeat path in arm_smmu_cmdq_issue_cmdlist() with an n > 0 check so we never inspect cmds[0] on the bare-SYNC flush emitted by arm_smmu_cmdq_batch_add_cmd_p() when the next command is unsupported by the batch's pre-selected cmdq. - Drop the carried Reviewed-by tags now that the patch shape has changed; re-review appreciated. Changes since v2: - Split into a 3-patch series (refactor / detect / apply) to keep each step small and bisectable. - Move the classifier to arm-smmu-v3.h as static inline so the iommufd file can share it. - Add arm_vsmmu_can_batch_cmd() to split iommufd batches at "needs repeating" transitions so the per-batch decision based on the first command stays correct under mixed user input. - Spell out in the commit message why detection is via DT and not via IIDR/ACPI. Changes since v1: - Detect the erratum from the existing "nvidia,tegra264-smmu" compatible instead of adding a new property. - Centralise the doubling at the CMDQ submission layer and only apply it to CFGI/TLBI (not ATC_INV). - Drop the binding/dtsi patches accordingly. Ashish Mhetre (2): iommu/arm-smmu-v3: Introduce CFGI/TLBI-repeat workaround infrastructure iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 Nicolin Chen (1): iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Documentation/arch/arm64/silicon-errata.rst | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 15 ++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 63 +++++++++++++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 15 +++++ 4 files changed, 83 insertions(+), 12 deletions(-) base-commit: b9810cd75b9fb56a3425d391cba3f608502bd474 -- 2.50.1