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[89.11.176.184]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b01cab1888sm4161884e87.83.2026.07.15.05.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 05:29:18 -0700 (PDT) From: "Ola Chr. Vaage" To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Thierry Reding , Jonathan Hunter , Mikko Perttunen , linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, "Ola Chr . Vaage" , "Ola Chr. Vaage" Subject: Re: [PATCH v1 6/6] pwm: tegra: Implement .get_state() Date: Wed, 15 Jul 2026 14:28:48 +0200 Message-ID: <20260715122914.2815081-1-o.c.vage@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <33b13f17d7135923d08e2ff40c867803e19609b9.1784030076.git.ukleinek@kernel.org> References: <33b13f17d7135923d08e2ff40c867803e19609b9.1784030076.git.ukleinek@kernel.org> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hello Uwe, On Tue, Jul 14, 2026 at 02:02:40PM +0200, Uwe Kleine-König wrote: > Subject: [PATCH v1 6/6] pwm: tegra: Implement .get_state() I tested this on a Jetson Orin NX (Tegra234), the board from my divider truncation report, driving a fan on the 32a0000 PWM instance. The board runs NVIDIA's L4T 5.15 kernel, so I backported the patch onto that tree: .get_state() returns void there, pwmchip_parent(chip) becomes the driver's device pointer, and the per-SoC enable_reg / scale_width indirection collapses to the fixed CSR layout (that tree predates the Tegra264 restructure). The decode logic is unchanged from your patch. The tree also carries my divider change from the other thread, which is why the achieved periods in the table differ from what your base would program. Procedure: apply a state through the pwm sysfs interface, read the CSR register and the clock rate independently (/dev/mem and clk_summary), then unexport/re-export the channel so pwm_device_request() invokes .get_state(), and compare the reported state against values computed from the raw register: applied period/duty/enabled readback computed from CSR+clk 45334/20000/1 46432/20496/1 46432/20496/1 500000/250000/1 481883/240942/1 481883/240942/1 5000/2500/1 5020/2510/1 5020/2510/1 45334/45334/1 (100% duty) 46432/46432/1 46432/46432/1 45334/20000/0 enabled=0 enabled=0 The clock rate varied across the cases (3.19, 11.03 and 102 MHz), so the scale field was exercised at several values, and the 100% duty case reads the full 9-bit duty field (pwm0 = 256). The readback consistently reports the achieved hardware state rather than the requested one. One limitation of my backport, not your code: in the disabled case I only set state->enabled = false instead of zeroing the whole struct, so I did not verify the period/duty values your version reports for a disabled channel. Tested-by: Ola Chr. Vaage Best regards Ola