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Mon, 27 Jul 2026 19:55:05 -0700 (PDT) From: Abraham Zukor To: Jon Hunter , Mark Brown , Laxman Dewangan Cc: Thierry Reding , linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] spi: tegra114: initialize native chip selects inactive Date: Mon, 27 Jul 2026 19:53:08 -0700 Message-ID: <20260728025503.162543-1-abe@maticrobots.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: <20260725042944.1204409-1-abe@maticrobots.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On 27/07/2026 13:07, Jon Hunter wrote: > What about the case where the SPI devices CS is active high or a > mixture of the two? An all-active-high bus is the case the window gets right today: probe writes zero to the field, so an active-high CS idles deasserted and an active-low one sits asserted. This patch inverts that. No single constant covers a mixed board - one polarity or the other is asserted until tegra_spi_setup() runs for that device - so the question is which default is the right one, and active low is what the SPI core assumes when a device says nothing. Setting that default in probe and correcting it per device later is an established model for controllers with a programmable CS idle level. f9c6ef6cfe9c ("spi/xilinx: Support for spi mode CS_HIGH") added both halves at once, to a driver that does advertise SPI_CS_HIGH: xilinx_spi_probe() sets cs_inactive to all ones, and xilinx_spi_setup_transfer() clears the bit for an SPI_CS_HIGH device. The changelog gives the rationale: The core controls the chip select lines individually. By default, all the lines are consider active_low. After spi_setup_transfer, it has its real value. tegra_qspi_probe() ends up in the same state by another route: def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL drives the line high in software CS mode, so its native chip select idles deasserted before setup runs, even though its CS_POL_INACTIVE bits are zero like ours. That is a single line on Tegra234, where cs_count is 1, so it never meets the multi-CS case, but the idle level it picks is the active-low one. Others leave the reset polarity alone rather than overwrite it - sifive_spi_probe() saves and restores CSDEF, bcm63xx_hsspi_probe() reads GLOBAL_CTRL_CS_POLARITY back into bs->cs_polarity. tegra_spi_probe() does neither: it writes the field, and writes zeros. The Tegra234 TRM documents all CS_POL_INACTIVE bits as one after reset, which is the inactive level for an active-low device, so probe is discarding a value that suits the common case for one that does not. Thanks, Abe