From: Jon Hunter <jonathanh@nvidia.com>
To: Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
"Thierry Reding" <thierry.reding@kernel.org>,
Sheetal <sheetal@nvidia.com>, <peter.ujfalusi@linux.intel.com>
Cc: <linux-sound@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Jon Hunter <jonathanh@nvidia.com>, <stable@vger.kernel.org>
Subject: [PATCH 3/4] ASoC: tegra: Sort ADMAIF register defaults
Date: Fri, 21 Aug 2026 16:37:33 +0100 [thread overview]
Message-ID: <20260821153734.158426-4-jonathanh@nvidia.com> (raw)
In-Reply-To: <20260821153734.158426-1-jonathanh@nvidia.com>
Commit 4b05ccb17f92 ("regcache: Sort the local copy of an unsorted
reg_defaults array") exposed an issue in the Tegra ADMAIF driver and now
the following warning is observed:
tegra210-admaif 290f000.admaif: Driver needs fixing: Unsorted
reg_defaults, sorting the copy
This warning occurs because register defaults in the structures
tegra186_admaif_reg_defaults and tegra264_admaif_reg_defaults are not
specified in ascending order which is required by regmap. Fix this by
sorting the register defaults according to their address. Note that in
order to do this it is necessary to split the macro ADMAIF_REG_DEFAULTS
into separate RX and TX macros to the RX and TX registers.
Fixes: f74028e159bb ("ASoC: tegra: Add Tegra210 based ADMAIF driver")
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
sound/soc/tegra/tegra210_admaif.c | 208 ++++++++++++++++++++----------
1 file changed, 138 insertions(+), 70 deletions(-)
diff --git a/sound/soc/tegra/tegra210_admaif.c b/sound/soc/tegra/tegra210_admaif.c
index 7299c6bfcf15..87e898cc35e4 100644
--- a/sound/soc/tegra/tegra210_admaif.c
+++ b/sound/soc/tegra/tegra210_admaif.c
@@ -26,94 +26,162 @@
#define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
-#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base, cif_ctrl) \
+#define RX_REG_DEFAULTS(id, rx_ctrl, rx_base, cif_ctrl) \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), cif_ctrl }, \
- { CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }, \
+ { CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }
+
+#define TX_REG_DEFAULTS(id, tx_ctrl, tx_base, cif_ctrl) \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), cif_ctrl }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }
-#define ADMAIF_REG_DEFAULTS(id, chip) \
- REG_DEFAULTS((id) - 1, \
+#define ADMAIF_RX_REG_DEFAULTS(id, chip) \
+ RX_REG_DEFAULTS((id) - 1, \
chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
+ chip ## _ADMAIF_RX_BASE, \
+ chip ## _ADMAIF_CIF_REG_DEFAULT)
+
+#define ADMAIF_TX_REG_DEFAULTS(id, chip) \
+ TX_REG_DEFAULTS((id) - 1, \
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX_BASE, \
- chip ## _ADMAIF_RX_BASE, \
chip ## _ADMAIF_CIF_REG_DEFAULT)
static const struct reg_default tegra186_admaif_reg_defaults[] = {
- {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
- ADMAIF_REG_DEFAULTS(1, TEGRA186),
- ADMAIF_REG_DEFAULTS(2, TEGRA186),
- ADMAIF_REG_DEFAULTS(3, TEGRA186),
- ADMAIF_REG_DEFAULTS(4, TEGRA186),
- ADMAIF_REG_DEFAULTS(5, TEGRA186),
- ADMAIF_REG_DEFAULTS(6, TEGRA186),
- ADMAIF_REG_DEFAULTS(7, TEGRA186),
- ADMAIF_REG_DEFAULTS(8, TEGRA186),
- ADMAIF_REG_DEFAULTS(9, TEGRA186),
- ADMAIF_REG_DEFAULTS(10, TEGRA186),
- ADMAIF_REG_DEFAULTS(11, TEGRA186),
- ADMAIF_REG_DEFAULTS(12, TEGRA186),
- ADMAIF_REG_DEFAULTS(13, TEGRA186),
- ADMAIF_REG_DEFAULTS(14, TEGRA186),
- ADMAIF_REG_DEFAULTS(15, TEGRA186),
- ADMAIF_REG_DEFAULTS(16, TEGRA186),
- ADMAIF_REG_DEFAULTS(17, TEGRA186),
- ADMAIF_REG_DEFAULTS(18, TEGRA186),
- ADMAIF_REG_DEFAULTS(19, TEGRA186),
- ADMAIF_REG_DEFAULTS(20, TEGRA186)
+ ADMAIF_RX_REG_DEFAULTS(1, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(2, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(3, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(4, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(5, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(6, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(7, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(8, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(9, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(10, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(11, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(12, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(13, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(14, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(15, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(16, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(17, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(18, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(19, TEGRA186),
+ ADMAIF_RX_REG_DEFAULTS(20, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(1, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(2, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(3, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(4, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(5, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(6, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(7, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(8, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(9, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(10, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(11, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(12, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(13, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(14, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(15, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(16, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(17, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(18, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(19, TEGRA186),
+ ADMAIF_TX_REG_DEFAULTS(20, TEGRA186),
+ {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static const struct reg_default tegra210_admaif_reg_defaults[] = {
- {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003},
- ADMAIF_REG_DEFAULTS(1, TEGRA210),
- ADMAIF_REG_DEFAULTS(2, TEGRA210),
- ADMAIF_REG_DEFAULTS(3, TEGRA210),
- ADMAIF_REG_DEFAULTS(4, TEGRA210),
- ADMAIF_REG_DEFAULTS(5, TEGRA210),
- ADMAIF_REG_DEFAULTS(6, TEGRA210),
- ADMAIF_REG_DEFAULTS(7, TEGRA210),
- ADMAIF_REG_DEFAULTS(8, TEGRA210),
- ADMAIF_REG_DEFAULTS(9, TEGRA210),
- ADMAIF_REG_DEFAULTS(10, TEGRA210)
+ ADMAIF_RX_REG_DEFAULTS(1, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(2, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(3, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(4, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(5, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(6, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(7, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(8, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(9, TEGRA210),
+ ADMAIF_RX_REG_DEFAULTS(10, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(1, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(2, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(3, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(4, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(5, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(6, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(7, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(8, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(9, TEGRA210),
+ ADMAIF_TX_REG_DEFAULTS(10, TEGRA210),
+ {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static const struct reg_default tegra264_admaif_reg_defaults[] = {
- {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003},
- ADMAIF_REG_DEFAULTS(1, TEGRA264),
- ADMAIF_REG_DEFAULTS(2, TEGRA264),
- ADMAIF_REG_DEFAULTS(3, TEGRA264),
- ADMAIF_REG_DEFAULTS(4, TEGRA264),
- ADMAIF_REG_DEFAULTS(5, TEGRA264),
- ADMAIF_REG_DEFAULTS(6, TEGRA264),
- ADMAIF_REG_DEFAULTS(7, TEGRA264),
- ADMAIF_REG_DEFAULTS(8, TEGRA264),
- ADMAIF_REG_DEFAULTS(9, TEGRA264),
- ADMAIF_REG_DEFAULTS(10, TEGRA264),
- ADMAIF_REG_DEFAULTS(11, TEGRA264),
- ADMAIF_REG_DEFAULTS(12, TEGRA264),
- ADMAIF_REG_DEFAULTS(13, TEGRA264),
- ADMAIF_REG_DEFAULTS(14, TEGRA264),
- ADMAIF_REG_DEFAULTS(15, TEGRA264),
- ADMAIF_REG_DEFAULTS(16, TEGRA264),
- ADMAIF_REG_DEFAULTS(17, TEGRA264),
- ADMAIF_REG_DEFAULTS(18, TEGRA264),
- ADMAIF_REG_DEFAULTS(19, TEGRA264),
- ADMAIF_REG_DEFAULTS(20, TEGRA264),
- ADMAIF_REG_DEFAULTS(21, TEGRA264),
- ADMAIF_REG_DEFAULTS(22, TEGRA264),
- ADMAIF_REG_DEFAULTS(23, TEGRA264),
- ADMAIF_REG_DEFAULTS(24, TEGRA264),
- ADMAIF_REG_DEFAULTS(25, TEGRA264),
- ADMAIF_REG_DEFAULTS(26, TEGRA264),
- ADMAIF_REG_DEFAULTS(27, TEGRA264),
- ADMAIF_REG_DEFAULTS(28, TEGRA264),
- ADMAIF_REG_DEFAULTS(29, TEGRA264),
- ADMAIF_REG_DEFAULTS(30, TEGRA264),
- ADMAIF_REG_DEFAULTS(31, TEGRA264),
- ADMAIF_REG_DEFAULTS(32, TEGRA264)
+ ADMAIF_RX_REG_DEFAULTS(1, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(2, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(3, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(4, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(5, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(6, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(7, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(8, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(9, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(10, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(11, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(12, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(13, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(14, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(15, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(16, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(17, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(18, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(19, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(20, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(21, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(22, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(23, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(24, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(25, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(26, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(27, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(28, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(29, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(30, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(31, TEGRA264),
+ ADMAIF_RX_REG_DEFAULTS(32, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(1, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(2, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(3, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(4, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(5, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(6, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(7, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(8, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(9, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(10, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(11, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(12, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(13, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(14, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(15, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(16, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(17, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(18, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(19, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(20, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(21, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(22, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(23, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(24, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(25, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(26, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(27, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(28, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(29, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(30, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(31, TEGRA264),
+ ADMAIF_TX_REG_DEFAULTS(32, TEGRA264),
+ {(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)
--
2.43.0
next prev parent reply other threads:[~2026-08-21 15:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-21 15:37 [PATCH 0/4] ASoC: tegra: Fixes for issues exposed in Linux v7.2 Jon Hunter
2026-08-21 15:37 ` [PATCH 1/4] ASoC: tegra: Fix the I2S enable default value Jon Hunter
2026-08-21 15:37 ` [PATCH 2/4] ASoC: tegra: Fix the MIXER " Jon Hunter
2026-08-21 15:37 ` Jon Hunter [this message]
2026-08-21 15:37 ` [PATCH 4/4] ASoC: tegra: Sort MBDRC register defaults Jon Hunter
2026-08-21 17:09 ` [PATCH 0/4] ASoC: tegra: Fixes for issues exposed in Linux v7.2 Mark Brown
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