Linux Tegra architecture development
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From: Ketan Patil <ketanp@nvidia.com>
To: <krzk@kernel.org>, <thierry.reding@kernel.org>, <jonathanh@nvidia.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	Ketan Patil <ketanp@nvidia.com>
Subject: [PATCH 0/3] memory: tegra: Refactor Tegra264 mc-err code
Date: Thu, 3 Sep 2026 18:25:17 +0000	[thread overview]
Message-ID: <20260903182520.950555-1-ketanp@nvidia.com> (raw)

The MC and HUB error-logging paths on Tegra264 used large switch
statements that interleaved register offsets, bit positions and
decoding parameters for each error type, which made them hard to read
and review. This patchset refactors these paths without intending any
functional change to error decoding behavior.

Ketan Patil (3):
  memory: tegra: Use named defines for Tegra264 MC apertures
  memory: tegra: Parameterise Tegra264 MCF slice bound
  memory: tegra: Refactor Tegra264 mc-err code

 drivers/memory/tegra/tegra264.c | 376 ++++++++++++++++++++------------
 1 file changed, 237 insertions(+), 139 deletions(-)

-- 
2.43.0


             reply	other threads:[~2026-09-03 18:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-03 18:25 Ketan Patil [this message]
2026-09-03 18:25 ` [PATCH 1/3] memory: tegra: Use named defines for Tegra264 MC apertures Ketan Patil
2026-09-03 18:25 ` [PATCH 2/3] memory: tegra: Parameterise Tegra264 MCF slice bound Ketan Patil
2026-09-03 18:25 ` [PATCH 3/3] memory: tegra: Refactor Tegra264 mc-err code Ketan Patil

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