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Wed, 23 Sep 2026 00:19:16 -0700 From: Manikanta Maddireddy To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , "Krzysztof Wilczynski" , Bjorn Helgaas , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Vidya Sagar , Niklas Cassel , , , Manikanta Maddireddy Subject: [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Date: Wed, 23 Sep 2026 12:47:06 +0530 Message-ID: <20260923071706.1134320-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923071706.1134320-1-mmaddireddy@nvidia.com> References: <20260923071706.1134320-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002313:EE_|MW4PR12MB7432:EE_ X-MS-Office365-Filtering-Correlation-Id: a9bcdecd-c2f1-438d-3b04-08df1943072f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|23010399003|22082099003|18002099003|56012099006|11063799006|10067099003; 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Signed-off-by: Manikanta Maddireddy --- .../controller/dwc/pcie-designware-debugfs.c | 56 +++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c index be0b84665c9e..daabc6ff0d85 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -31,14 +31,8 @@ #define ERR_INJ_ENABLE_REG 0x30 -#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc - -#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 -#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24) -#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16) #define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) #define EVENT_COUNTER_STATUS BIT(7) -#define EVENT_COUNTER_ENABLE GENMASK(4, 2) #define PER_EVENT_ON 0x3 #define PER_EVENT_OFF 0x1 @@ -356,11 +350,15 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata, { u32 val; - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); - val &= ~EVENT_COUNTER_ENABLE; - FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no); - FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); + val &= ~EVENT_COUNTER_ENABLE_MASK; + FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, + event_list[pdata->idx].group_no); + FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val, + event_list[pdata->idx].event_no); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); } static ssize_t counter_enable_read(struct file *file, char __user *buf, @@ -375,13 +373,16 @@ static ssize_t counter_enable_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val = FIELD_GET(EVENT_COUNTER_STATUS, val); if (val) - pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n"); + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter Enabled\n"); else - pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n"); + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter Disabled\n"); return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); } @@ -401,13 +402,15 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); if (enable) - val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); + val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_ON); else - val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); + val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_OFF); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); /* * While enabling the counter, always read the status back to check if @@ -416,7 +419,7 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf, */ if (enable) { val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + - RAS_DES_EVENT_COUNTER_CTRL_REG); + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) { mutex_unlock(&rinfo->reg_event_lock); return -EOPNOTSUPP; @@ -440,7 +443,8 @@ static ssize_t counter_lane_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); mutex_unlock(&rinfo->reg_event_lock); val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val); pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val); @@ -463,9 +467,11 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL); FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); mutex_unlock(&rinfo->reg_event_lock); return count; @@ -483,9 +489,11 @@ static ssize_t counter_value_read(struct file *file, char __user *buf, mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + + PCIE_RAS_DES_EVENT_COUNTER_DATA); mutex_unlock(&rinfo->reg_event_lock); - pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val); + pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, + "Counter value: %d\n", val); return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index f70b7da97e07..4d55339750f0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -276,7 +276,6 @@ #define EVENT_COUNTER_ENABLE_ALL 0x7 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) -#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 -- 2.34.1