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Wed, 23 Sep 2026 00:26:28 -0700 From: Manikanta Maddireddy To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , "Krzysztof Wilczynski" , Bjorn Helgaas , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Vidya Sagar , Niklas Cassel , , , Manikanta Maddireddy Subject: [PATCH 3/3] PCI: tegra194: Notify Endpoint functions on PERST# assert Date: Wed, 23 Sep 2026 12:55:54 +0530 Message-ID: <20260923072554.1141864-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923072554.1141864-1-mmaddireddy@nvidia.com> References: <20260923072554.1141864-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF000264B0:EE_|SJ1PR12MB6074:EE_ X-MS-Office365-Filtering-Correlation-Id: eae0bee6-e070-42c7-7be2-08df19440b50 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|23010399003|36860700016|10067099003|56012099006|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qbdb60tufGa4LFpba7IyuC7gLsRM9iZC4s+Db5E8Mgxu57kmG7Ry/PElYdxXXZ0cFjZzQkLbQ6EdZeVxV2BC6Kv9esaW3iB1SEq15zJoiXlLEQ/LruO70cHdChRHh8o97kVlKaA6RlK0EBUXc1D/BIZ08oELsHeZnvrIS/tXud0/GDKBi8s0EQPA7X2Am8jSGsIZf1Ai9viRWKFE9/UMQajwK3YMHDJ3oO5LzdrulVBUEYN5xoqICW8t7ZGfdhYMqsbuzUakcoZVXGqZydfz3O77bjRWVaXckSCklNbfr8cC46UV3VBZoLIulYUgsxVBh1OXptinv9+y31fg0Ysdf+4OkebkXgBsMAhJhfLvhg1GGWSGKqrDVqP97jDEVH0UmR824tRI4TzjgWllL1UxRURkLU6S3V80HTjt1bia4Hyb6oz8PtCPvFtSwmBF2k68 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 07:26:54.6825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eae0bee6-e070-42c7-7be2-08df19440b50 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF000264B0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6074 Tegra Endpoint mode powers the controller down when the host asserts PERST#. EPF drivers must be told about link down before that happens, otherwise remove while PERST# is asserted can free EPC resources while EPF work is still active. Use pci_epc_linkdown() directly in the PERST# assert path. It is a software-only EPF notification and avoids dw_pcie_ep_linkdown(), which reinitializes non-sticky DWC registers and touches DBI while the host REFCLK may be disappearing. Keep pci_epc_deinit_notify() in the PERST# deassert path, after core reset is deasserted, because EPF deinit callbacks can clear BARs and therefore need register access. If remove runs while the controller is already powered down, pex_ep_event_pex_rst_assert() returns because ep_state is disabled; that is safe because the link-down notification was sent at the earlier PERST# assert. The final dw_pcie_ep_deinit() does not require Tegra register access today: Tegra uses its own MSI-X address-match window instead of the DWC MSI iATU, and the supported DTs do not register a DWC eDMA device. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-tegra194.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index dd3f4c30ba52..3e9d46850a78 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1724,6 +1724,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) { + struct dw_pcie_ep *ep = &pcie->pci.ep; u32 val; int ret; @@ -1745,6 +1746,8 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (ret) dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", val, ret); + pci_epc_linkdown(ep->epc); + /* * Deassert LTSSM state to stop the state toggling between * Polling and Detect. @@ -1913,7 +1916,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) } /* Perform cleanup that requires refclk and core reset deasserted */ - pci_epc_deinit_notify(pcie->pci.ep.epc); + pci_epc_deinit_notify(ep->epc); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val &= ~PORT_LOGIC_SPEED_CHANGE; -- 2.34.1