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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-182a16488dbsm665948c88.3.2026.10.15.11.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 11:30:24 -0700 (PDT) Date: Thu, 15 Oct 2026 11:30:19 -0700 From: Jonathan Cameron To: Srirangan Madhavan Cc: mark.rutland@arm.com, lpieralisi@kernel.org, sudeep.holla@kernel.org, conor@kernel.org, jic23@kernel.org, catalin.marinas@arm.com, will@kernel.org, andre.przywara@arm.com, aneesh.kumar@kernel.org, Souvik.Chakravarty@arm.com, treding@nvidia.com, jonathanh@nvidia.com, bence.csokas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v4 2/2] cache: add SMCCC-backed cache invalidate provider Message-ID: <20261015113019.000050e3@oss.qualcomm.com> In-Reply-To: <20261013070205.3566865-3-smadhavan@nvidia.com> References: <20261013070205.3566865-1-smadhavan@nvidia.com> <20261013070205.3566865-3-smadhavan@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDA3MyBTYWx0ZWRfX6HQLoV2F2FN6 ZMUcOl/u9oWFxoyARnRPd7zWIk+EBxF4Ab5t2IaCjX/idxW1BrCyVTPJYaCfHGjm9V6ZciMA1or lJATtFZAwKcC5KhilFj+sxaYuz9dc4I= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDA3MyBTYWx0ZWRfX7x7ayDbb/ee4 +VR3CwMVY0lKWuS/aiE/MmhlU3AyTZk4vEN7lSSTsdMTLsKCA/6FkzF1ZKfPXqt+R8ebgqbZyuf egGMU0nkXGeZd739A9BoX2eh6Zn9hoqECpuWVKvVupoQxV3Hh5oFQsp9lSQ1D89qFLTv/t2GZ1O sfhl2BJnvN/r+xKYid8u5Lkm7wBz/rU3l20PJnIuoLBNnsFVcGOAmFCkdFNr+iHDkbUIxmgQX0w NVkFbMBVyR/9NjWmzZ/yDDilY0HdG5ZOwTWLEJdBluSX6L3IMbVdxcUpp9qfcJVcsSdDl6zBifT wOwVM0mKyhHVFMlM9Nrrdb4gTCZ4THvMQoE8R8b/XfPrO20Bd1tpJ+zKIhdlfoL/MIRlsHnISWU KYqVo3kPSh0cu7M4J083yKEdNd0yKMqqK8TvSRJjsmY539KlNJHQdG0FdlogOnanX3s9EWNgqRy 1r0hdgkdNzWGqaSmwJw== X-Authority-Analysis: v=2.4 cv=BNMmP1QG c=1 sm=1 tr=0 ts=6ad11bc2 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=Ikd4Dj_1AAAA:8 a=EUspDBNiAAAA:8 a=24jIKSGD-yZtkObPp0AA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: VuisLBBpzi-nDgYpAkJNsy1Rm7OpDTUi X-Proofpoint-ORIG-GUID: VuisLBBpzi-nDgYpAkJNsy1Rm7OpDTUi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-14_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150073 On Tue, 13 Oct 2026 07:02:05 +0000 Srirangan Madhavan wrote: > Add a cache maintenance provider for the cache clean+invalidate interface > defined by Arm DEN0028 v1.7. > > Register the interface attributes function as an SMCCC device and bind the > provider through the SMCCC bus. The provider reads the firmware attributes > during probe and serializes cache maintenance calls. It handles transient > BUSY and RATE_LIMITED responses with bounded retries. It also registers > with the generic cache coherency framework used by memregion callers. > > Signed-off-by: Srirangan Madhavan I'm fine with the changes to put it on the bus and Andre's suggestion to drop the latency value handling. So with that done Reviewed-by: Jonathan Cameron I'd probably not have bothered with the mutex_destroy() given limited utility vs code added (I mind that less if devm is appropriate, but doing that here would be messy). If we ever see a use of that after the destroy then something exceedingly weird is going on! Anyhow, doesn't really matter either way. Jonathan