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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zu4zriHt8TYN0zfe6Y/vbFaT40IqIAWeNQXyb+vKVmng0cj+3Ux7EtUiET/90DxgKUu0koilaagkzH6OSHCJV1YkZfvZMQqI1w74jAO7hYwsY0N6JvvWllAI97Y+/5tj+AdR3XIJfSgcoJIs1A9xUgQxkBfnEw7g0NF+pfYAxZH1CAv/EWAoL1svHa8roYhifbg1F1bvhUIgCdEAARNNEBTzr0HWIu/YhgOlXtQoou+fcR3QqvKpbUNkfFFIYpk7bnD13cb02tbkHi9OOlhP9FLzQUhYx+eKGKCJ7D+hsmlxJJKf+Z9DQod3l1t9lDxvWpNKUeLHHc7AkREPxPsaUaB5VuMoSLTneYkOagDZeNAgocOwHJSnP4BjBSbYqvZ1INGjvP9noGzgwCAeRExjyT8ZxSbh6R4rsMBmerjqZ5I0jnIUwLXxiJ0wncAl4d+N X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 13:25:48.3489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 005cce58-6823-48d1-2419-08df2b88fde5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0002457A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6737 tegra_qspi_handle_timeout() captures a "lost IRQ" FIFO status snapshot when the ISR cache is empty on entry but QSPI_TRANS_STATUS shows the transfer completed. After masking the controller IRQ and draining the workqueue with cancel_work_sync(), it re-loads the ISR cache with smp_load_acquire(): if the drain observed a real ISR completion, the refreshed cache holds ISR-published status_reg, tx_status and rx_status that reflect the true hardware error state at IRQ time. However, when both cache and snapshot are set, the code keeps the refreshed value in the local status variable but then unconditionally publishes the pre-drain lost_fifo_status / lost_tx_status / lost_rx_status snapshot into tqspi->status_reg / tx_status / rx_status via the lost_irq_snapshot branch. That snapshot is racy: if the ISR fires on another CPU between our live QSPI_TRANS_STATUS read and our live QSPI_FIFO_STATUS snapshot, the ISR W1Cs the hardware error bits before we sample them, so the snapshot may contain zeroed error fields. Overwriting the ISR-published values with these zeros makes the manual completion handler downstream silently accept a transfer that actually reported a FIFO error. Clear lost_irq_snapshot when the refreshed cache is non-zero, so the ISR-published status wins over the pre-drain snapshot in that case. The lost-IRQ path (refreshed == 0 && live QSPI_RDY set) is unaffected. Fixes: 1ff82c13ea94 ("spi: tegra210-quad: Cache TRANS_STATUS in ISR for timeout handler") Reported-by: Carol Soto Link: https://github.com/NVIDIA/NV-Kernels/pull/579 Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index d8cca3aa276b..4a5933d8112c 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1260,8 +1260,17 @@ static int tegra_qspi_handle_timeout(struct tegra_qspi *tqspi) * loaded the cache but before we masked). */ refreshed = smp_load_acquire(&tqspi->trans_status); - if (refreshed) + if (refreshed) { status = refreshed; + /* + * The drain observed a real ISR completion. Prefer the + * ISR-published status_reg / tx_status / rx_status over + * the pre-drain lost-IRQ snapshot, which may have been + * taken after the ISR W1C-ed the hardware error bits and + * therefore holds cleared values. + */ + lost_irq_snapshot = false; + } if (!(status & QSPI_RDY)) { retval = -ETIMEDOUT; -- 2.17.1