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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LbGpZqwL04+ZAV0R0rM4b8Ok4fn+itHNgpUaQ1HFz+uXKqR9L1n5efXt/4rzmusZ+Wjf19QAz3Z7ro8/I7IcYnsxbTqoZWGl1uYZqiu+cVAO4mhPn196lgeQfllSsFbVQPJOF2Nex+vDga+iJ+TBdiDmJvNCms5GrFdRMRE14wrc+kE1V7xCkW2F+I/p6ilsZ7smLI4PaCOlY5JuES2nM8Nxc8j2w7DQ7IqUVJXG68TzaEZzP9NAl2vWk/6iccaTSiDRtkwzY1C1U88StNFoGwOmDxYgJ/IEOhU3xyBpMfp+FyJnfRYtCPEibTUeR81uLQTUkLRzn0kyoL4mFmUPdrrGMRxQRpeheDpvvTkJiHt5z4CHbiq99JSEoyokrEmpfKiwBMFYdCjK05MbgyPE5orDwpyo/WKYcmlbkFC+mW/luhBLQvJMshLJFjMod/8a X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 13:25:50.0169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28a5f86c-0f38-4f21-d7eb-08df2b88fece X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF000264B3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999140 tegra_qspi_start_dma_based_transfer() maps the client TX/RX buffers with dma_map_single() via tegra_qspi_dma_map_xfer(). The matching unmap only happens in handle_dma_based_xfer(), which runs from the interrupt bottom half. When wait_for_completion_timeout() expires and tegra_qspi_handle_timeout() cannot establish that the hardware finished, it returns an error without the bottom half ever having run. Both transfer paths then abort the transfer with tegra_qspi_dma_stop(), reset the controller and clear curr_xfer, but never unmap the buffers. Every genuine transfer timeout therefore leaks the streaming DMA mappings for that chunk, which gradually exhausts the IOVA space on systems with an IOMMU in front of QSPI. Unmap the transfer after stopping DMA on both timeout error paths. The unmap is placed after tegra_qspi_dma_stop() so the DMA engine is quiesced before the mappings go away. The recovery paths that do reach handle_dma_based_xfer() are unaffected: that function always returns IRQ_HANDLED, so tegra_qspi_handle_timeout() reports success and the caller's error path is not taken, leaving the existing single unmap in place. Fixes: 921fc1838fb0 ("spi: tegra210-quad: Add support for Tegra210 QSPI controller") Cc: stable@vger.kernel.org Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 4a5933d8112c..b77ad6990e7c 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1488,10 +1488,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, dev_err(tqspi->dev, "transfer timeout\n"); /* Abort transfer by resetting pio/dma bit */ - if (tqspi->is_curr_dma_xfer) + if (tqspi->is_curr_dma_xfer) { tegra_qspi_dma_stop(tqspi); - else + tegra_qspi_dma_unmap_xfer(tqspi, xfer); + } else { tegra_qspi_pio_stop(tqspi); + } /* Reset controller if timeout happens */ tegra_qspi_reset(tqspi); @@ -1605,8 +1607,10 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, WARN_ON(1); dev_err(tqspi->dev, "transfer timeout\n"); - if (tqspi->is_curr_dma_xfer) + if (tqspi->is_curr_dma_xfer) { tegra_qspi_dma_stop(tqspi); + tegra_qspi_dma_unmap_xfer(tqspi, xfer); + } tegra_qspi_handle_error(tqspi); ret = -EIO; -- 2.17.1