From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADDDC4E36C8; Fri, 16 Oct 2026 16:07:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792166824; cv=none; b=My3SUgcrC/6flwcXx3WKW+9x5b+hk83u0h1bqVbUC9/jaAn6hwwtVmdMRuLtbDegyE3tOFwX3BjLrEBRbTgCK92qu1sXlLYJ6C08ttv5xVICzpiy91fFWjOzKWdVAPg8H6qQisP2wNXsATycOse74N7gj3MpuV3JLNB9nlcbR38= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792166824; c=relaxed/simple; bh=vMSXYhWLHgCBvF6lMZjjuvJ/Yz8NwzSjsTqzWMLkl4g=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=RPbHaNMTBCq/Ic3bsgNU+utXrWbMLr+hiAzofkZ5AzzuP++c7PHtw0iQGgtHyDSymk2Hjo+5IijAtuDvFqO80PDXlSzHku+3aNWNecwB5H8T3xw9vaFuJEvbUXTuxW9AXPFPcChWb9qMC1ggLwBxB9KQ3NeGRjRO5A4zNyhpCak= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nvN/Wjbo; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nvN/Wjbo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20EC51F000C5; Fri, 16 Oct 2026 16:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792166823; bh=OruC+xVMUOjeQ0CCeCTlrwXSIelR6KAByPpIlRqyTfk=; h=From:To:Cc:Subject:Date; b=nvN/Wjbo5/6SUmUglC+oaP9HXTRyaQEx6EkhnKmEZc916Ohdgbyh63cA1IL+hyWwQ /I8vZpAU1qsb2NZcWq0rczGwe/cnY0xA2eQAGCJgSSvno5N2zsbXYzDF91lbqMRUkJ labZHPSKPsl1bpf4Q2UxA6bBGrHFzqYJZKMSmRhPrHTiwevwNrfW5Sg0c/NBsiwwTD /PMEG1kiMTjJhlSSbb0Pf0EqVRRNNyQgsgF4vLH2y+k7aBjQF3z691/iswQf1NWlzV xcuMRYTUeb5BkfBbfc9FCCWmjijS86ZCzj2NoS/oXlcvUUbuCYay82GhN4OvmrOA7E R+AKrhnfLmSMg== From: Sasha Levin To: Thierry Reding , Jonathan Hunter , Lyude Paul , Danilo Krummrich Cc: Sasha Levin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Courbot , Mikko Perttunen , Aaron Kling , Diogo Ivo , Svyatoslav Ryhel , Dmitry Osipenko , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/6] Keep the fuse clock enabled while the Tegra GPU is powered Date: Fri, 16 Oct 2026 12:06:53 -0400 Message-ID: <20261016160700.3831336-1-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since the GPU on the Jetson TX1 was enabled in its device tree, nouveau often fails to bring up the GM20B: BOOT_0 reads back garbage, PRI reads time out, or the first register reads stall until an SError. The GPU needs the fuse clock running while it is powered, but nothing keeps that clock enabled: the Tegra fuse driver only turns it on around its own fuse reads. This series describes the fuse clock in the GPU device tree nodes and has nouveau keep it enabled from before the GPU rail is turned on until after it is turned off. Patch 1 makes the fuse clock required by the binding and lists the exact clocks for each GPU. Patches 2-5 add it to the Tegra124, Tegra132, Tegra186 and Tegra210 device trees; Tegra194 already has it. Patch 6 makes nouveau use it. nouveau keeps treating the fuse clock as optional, so device trees that lack it continue to work as before. On eight Jetson TX1 devkits, the GPU failed to come up in 27 of 109 boots without the fix and in 11 of 291 with it; patch 6 has the details. Aaron Kling reported that a Jetson Nano that almost never loaded nouveau did so on 3 of 3 boots with v1. The Tegra124, Tegra132 and Tegra186 device tree changes have only been checked with dtbs_check. Changes in v2: - 1/6: List the exact clocks for each GPU, so that "fuse" cannot appear twice, and make the fuse clock required (Thierry). - 2/6, 3/6, 4/6: New. Add the fuse clock to the Tegra124, Tegra132 and Tegra186 GPUs as well (Thierry). - 5/6: Add a Fixes: tag, as the nouveau fix depends on it. - 6/6: Disable the fuse clock on power down even if disabling the regulator fails (sashiko). v1: https://lore.kernel.org/r/20261013145210.103565-1-sashal@kernel.org Sasha Levin (6): dt-bindings: gpu: nvidia,gk20a: Require the fuse clock ARM: tegra: Add the fuse clock to the Tegra124 GPU arm64: tegra: Add the fuse clock to the Tegra132 GPU arm64: tegra: Add the fuse clock to the Tegra186 GPU arm64: tegra: Add the fuse clock to the Tegra210 GPU drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered .../devicetree/bindings/gpu/nvidia,gk20a.yaml | 52 ++++++++++++++----- arch/arm/boot/dts/nvidia/tegra124.dtsi | 5 +- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 5 +- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 5 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +- .../gpu/drm/nouveau/include/nvkm/core/tegra.h | 1 + .../drm/nouveau/nvkm/engine/device/tegra.c | 22 +++++--- 7 files changed, 69 insertions(+), 26 deletions(-) base-commit: 70dd4ee72eb2d5793c62e71c14e3aba78e5a4e56 -- 2.53.0