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Wed, 28 Oct 2026 08:50:28 -0700 From: Johnny Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , "Prashant Gaikwad" , Stephen Boyd , Brian Masney , Jerome Brunet , "Douglas Anderson" , Aniruddha Rao , , , , CC: Johnny Liu Subject: [PATCH v2 3/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID Date: Wed, 28 Oct 2026 15:49:59 +0000 Message-ID: <20261028155000.1205739-4-johnliu@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028155000.1205739-1-johnliu@nvidia.com> References: <20261028155000.1205739-1-johnliu@nvidia.com> X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE942:EE_|SJ2PR12MB8953:EE_ X-MS-Office365-Filtering-Correlation-Id: 6849fab2-02ec-4289-aa64-08df350d5ab7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700016|82310400026|1800799024|23010399003|22082099003|18002099003|921020|11063799006|56012099006|261021121427099003|10067099003|261009223027099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SitDHgo5IbIE+FHL1xVgN5Ao9+RADGFve9pr/7JSsztMkCrilRln2tFhJDUbshDbnw7XlExr/vcwcivuhl6YnGeq2gg3+JRskSnSGrEaHEwUFwxVqKULg+q0AOdJn9NNfAZ2ObDhoyLbZCD8nCqvjKTyi5YzgUVuS6IIhCTPpnHiTenUlCCYLx3nqnDm1ff8Y21eORXfzyCsfalyXyzAESu9wjK2QQg7DOBsjEO5W4DxxW8CSqt7fPZoOb/QdGmI14ix+UBlQ6Iyff4x3rgCrzYD3sS4A4ZlVpp9pst/8NBSRrzFmGvUEwMOyuKeAtqW0yEf6kWL+4rVjaz2+8CmtYD9VKxTOwC/dxRwJ9ONqp35XrtLEBHW27VcrW4a555aW9QOcaa4TbU0hq1RSue/eXgLms8CnaeH9/ciAxKoDeCIsrEMhXrfDXCoEw2uMHgg X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2026 16:05:58.1228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6849fab2-02ec-4289-aa64-08df350d5ab7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE942.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8953 The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31, TEGRA238_CLK_EMC=43, TEGRA264_CLK_EMC=290). Add an emc_clk_id field to struct tegra_bpmp_soc and set it for Tegra234, Tegra238 and Tegra264. Tegra186 and Tegra194 have no EMC clock ID and leave it unset. Signed-off-by: Johnny Liu --- drivers/firmware/tegra/bpmp.c | 7 +++++++ include/soc/tegra/bpmp.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index beeb385870f5..06da888535dc 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -21,6 +21,10 @@ #include #include +#include +#include +#include + #include "bpmp-private.h" #define MSG_ACK BIT(0) @@ -1158,14 +1162,17 @@ static const struct tegra_bpmp_soc tegra186_soc = { static const struct tegra_bpmp_soc tegra234_soc = { TEGRA186_BPMP_SOC_COMMON, + .emc_clk_id = TEGRA234_CLK_EMC, }; static const struct tegra_bpmp_soc tegra238_soc = { TEGRA186_BPMP_SOC_COMMON, + .emc_clk_id = TEGRA238_CLK_EMC, }; static const struct tegra_bpmp_soc tegra264_soc = { TEGRA186_BPMP_SOC_COMMON, + .emc_clk_id = TEGRA264_CLK_EMC, }; #endif diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index f55db918ccb1..40e2db8e69cc 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -31,6 +31,7 @@ struct tegra_bpmp_soc { const struct tegra_bpmp_ops *ops; const struct tegra_bpmp_mbwt_soc *mbwt; unsigned int num_resets; + unsigned int emc_clk_id; }; struct tegra_bpmp_mb_data { -- 2.43.0