From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset
Date: Thu, 29 Oct 2026 16:47:39 -0700 [thread overview]
Message-ID: <230bad80-8e98-450a-a1b1-30356bf92c01@nvidia.com> (raw)
In-Reply-To: <auAZxpEJ6ojhu5gW@aschofie-mobl2.lan>
On 10/26/26 8:25 PM, Alison Schofield wrote:
> Hi Srirangan,
>
> Is above statement underselling the potential impact? The quiesce is
> cxl_rwsem.region held for write, so for the whole reset it also blocks
> region and decoder sysfs, region probe, poison list/inject/clear, sanitize
> and event record tracing, on every CXL device.
>
> Can the changelog say what it blocks and for how long?
>
> more below on the 'how long' ?
>
> snip
>
>
>> +static int cxl_reset_execute(struct pci_dev *pdev, int dvsec, u16 cap)
>> +{
>> + int rc;
>> +
>> + cxl_region_quiesce_lock();
>> + rc = cxl_reset_quiesced(pdev, dvsec, cap);
>> + cxl_region_quiesce_unlock();
> IIUC, this cxl_rwsem.region for write for the whole reset, including the
> Memory Clear wait, which can run to CXL_RESET_MAX_WAIT_MS (20 seconds) plus
> the cache flushes. That blocks all region activity, on every CXL device in
> the system, not just the one being reset. Does resetting one device need
> to stop all of it?
>
> snip
Thanks for pointing out the wider impact. I updated the changelog to
describe the operations blocked across CXL devices and to distinguish
the 20-second reset-wait cap from the full lock hold time.
I agree that the current approach does not establish that unrelated CXL
devices need to be blocked. For v16 I have retained the global lock,
because the current code has no narrower mechanism to exclude changes to
the affected region and decoder state
One option I can think of is to mark the endpoint as resetting while
holding the region lock, then release the lock during the reset wait.
Region operations involving that endpoint would check the marker before
changing state and return busy. After reset, we would reacquire the
region lock to restore state and clear the marker.
Does that seem like the right approach here? Or is there anything
simpler? I can either fold it into the reset series or add a follow up
changes to reduce the scope of this lock.
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-10-29 23:47 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-27 4:13 ` Alison Schofield
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-26 22:20 ` Dave Jiang
2026-10-27 6:23 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-26 22:32 ` Dave Jiang
2026-10-27 6:24 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-26 22:41 ` Dave Jiang
2026-10-27 6:31 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-26 22:56 ` Dave Jiang
2026-10-27 6:50 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-27 8:07 ` Li Ming
2026-10-29 3:19 ` Alison Schofield
2026-10-30 1:11 ` Srirangan Madhavan
2026-10-29 7:02 ` Li Ming
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-28 3:01 ` Li Ming
2026-10-30 1:23 ` Srirangan Madhavan
2026-10-30 1:33 ` Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-27 3:25 ` Alison Schofield
2026-10-29 23:47 ` Srirangan Madhavan [this message]
2026-10-27 4:32 ` Alison Schofield
2026-10-30 1:43 ` Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-27 3:56 ` Alison Schofield
2026-10-30 0:46 ` Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-27 2:41 ` Alison Schofield
2026-10-30 0:48 ` Srirangan Madhavan
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