Linux Tegra architecture development
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From: Mikko Perttunen <mperttunen@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	webgeek1234@gmail.com
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	Aaron Kling <webgeek1234@gmail.com>
Subject: Re: [PATCH v5] soc: tegra: fuse: speedo-tegra210: Add soc speedo 2
Date: Tue, 11 Nov 2025 17:32:04 +0900	[thread overview]
Message-ID: <2318763.irdbgypaU6@senjougahara> (raw)
In-Reply-To: <20251021-t210-actmon-p3-v5-1-e1ef5e93909d@gmail.com>

On Wednesday, October 22, 2025 12:11 PM Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
> 
> The Jetson Nano series of modules only have 2 emc table entries,
> different from other soc sku's. As the emc driver uses the soc speedo to
> populate the emc opp tables, add a new speedo id to uniquely identify
> this.
> 
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> Changes in v5:
> - Split series
> - Link to v4: https://lore.kernel.org/r/20250923-t210-actmon-v4-0-442d1eb6377c@gmail.com
> 
> Changes in v4:
> - Various cleanups in patch 5 as requested by review
> - Fix a couple typos in patch 4
> - Link to v3: https://lore.kernel.org/r/20250906-t210-actmon-v3-0-1403365d571e@gmail.com
> 
> Changes in v3:
> - In patch 5, don't fail mc probe if opp tables are missing
> - Add more mc bindings to patch 1
> - Add patch to use tegra210-mc bindings in the mc driver
> - Re-order series to align patches within a subsystem to each other
> - Link to v2: https://lore.kernel.org/r/20250903-t210-actmon-v2-0-e0d534d4f8ea@gmail.com
> 
> Changes in v2:
> - Assume 64-bit dram bus width in patch 4
> - Add dt-bindings patch to document the new properties on the
>   tegra210-emc node.
> - Link to v1: https://lore.kernel.org/r/20250828-t210-actmon-v1-0-aeb19ec1f244@gmail.com
> ---
>  drivers/soc/tegra/fuse/speedo-tegra210.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
> index a8cc3632977230fbfda0f8c3bfa7b7b25c2378fe..06c2bcbee5734207e3ebacb4057da2195f85321c 100644
> --- a/drivers/soc/tegra/fuse/speedo-tegra210.c
> +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
> @@ -97,6 +97,7 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
>  			break;
>  
>  		case 0x8F:
> +			sku_info->soc_speedo_id = 2;
>  			sku_info->cpu_speedo_id = 9;
>  			sku_info->gpu_speedo_id = 2;
>  			break;
> 
> ---
> base-commit: 211ddde0823f1442e4ad052a2f30f050145ccada
> change-id: 20251021-t210-actmon-p3-3810039d81e7
> prerequisite-change-id: 20250812-tegra210-speedo-470691e8b8cc:v4
> prerequisite-patch-id: d32dd215b54ac46086377c1ce2c8d53d746690c9
> 
> Best regards,
> 

While it can be argued this is upstream defining new speedo IDs non-authoritatively, I doubt there will be any new SoC speedo IDs coming otherwise, so seems like a fair approach to me.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>




  reply	other threads:[~2025-11-11  8:32 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  3:11 [PATCH v5] soc: tegra: fuse: speedo-tegra210: Add soc speedo 2 Aaron Kling via B4 Relay
2025-11-11  8:32 ` Mikko Perttunen [this message]
2025-11-14 16:19 ` Thierry Reding

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